Integrated circuit memory device with voltage boost

Details Integrated circuit memory device with voltage boost Integrated circuit memory device with voltage boost

1995-11-15

1996-12-24

Nguyen, Tan T.

Static information storage and retrieval

Addressing

Plural blocks or banks

36523006, 36518902, G11C 800

Patent

active

055879608

ABSTRACT:
An integrated circuit memory device is provided with a voltage boost facility. The voltage boost facility is used with a so-called divided wordline architecture, in which a wordline is divided into independently addressable sub-wordlines.

REFERENCES:
patent: 4977538 (1990-12-01), Anami et al.
patent: 5255224 (1993-10-01), Galbi et al.
patent: 5361237 (1994-11-01), Chishiki
patent: 5406526 (1995-04-01), Sugibayashi et al.
patent: 5416748 (1995-05-01), Fujita
1992 Symposium On VLSI Circuits Digest of Technical Papers, 1992, pp. 112-113, Noda, et al., "A Boosted Dual Word Line Decoding Scheme For 256MB Drams".
IEICE Transactions on Electronics, vol. E75C, Nov. 1992 Tokyo JP, pp. 1323-1332, Ooishi, et al. "A St (Stretchable Memory Matrix) Dram With Multivalued Addressing Scheme".
IBM Technical Disclosure Bulletin, vol. 30, No. 5, Oct. 1987, New York, US, pp. 378-379, "OWRD Line Segmenting With Two-Dimensional Decoding".
IBM Technical Disclosure Bulletin, vol. 26, No. 12, May 1984, New York, US, pp. 6652-6653, Ellis, "Decoded Isolation Device For Decoders".

Affiliated with

Also associated with

Rating

Integrated circuit memory device with voltage boost does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated circuit memory device with voltage boost, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit memory device with voltage boost will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1183459