Integrated circuit memory device, system and method having...

Details Integrated circuit memory device, system and method having... Integrated circuit memory device, system and method having...

2011-05-10

2011-05-10

Nguyen, Van Thu (Department: 2824)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S233100

Reexamination Certificate

active

07940598

ABSTRACT:
An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second clock frequency, output independent column and row control internal signals to a memory core in response to memory commands in the request packets. An integrated circuit memory device includes an interface having separate row and column decode logic circuits for providing independent sets of row and control signals. A row decode logic circuit includes a first row decode logic circuit that provides a first row control signal, such as a row address, and a second row decode logic circuit that provides a second row control signal. A column decode logic circuit includes a first column decode logic circuit that provides a first column control signal, such as a column address and a second column logic circuit that provides a second column control signal.

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Foreign Office Action, European Patent Office, European Patent Application No. 06 748 949.2-2210 filed Mar. 30, 2006, Dec. 17, 2008.

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