Integrated circuit memory device having interleaved read and...

Details Integrated circuit memory device having interleaved read and... Integrated circuit memory device having interleaved read and...

2002-07-25

2003-04-29

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Byte or page addressing

C365S230080, C365S189011, C365S189050

Reexamination Certificate

active

06556508

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an improved integrated memory circuit, with the capability of reading or programming continuously, pages of data, without any gaps, and to methods of operating same.
2. Description of the Prior Art
Semiconductor integrated memory circuit devices for storing data typically have been categorized as either volatile, in which the data is lost once the power is turned off, or non-volatile, in which the data is retained even after the power is turned off.
Non-volatile memories, comprising an array of non-volatile memory cells arranged in a plurality of rows and columns (or bit lines), can be categorized as either NAND or NOR type, referring to the manner in which the non-volatile memory cells are arranged in the array. Further, the non-volatile memory cells can be arranged to operate in a page mode manner, in which a page of data (typically 512 bytes) is stored in a plurality of latches (or plurality of page buffers) that are integrated with the memory circuit device. Reading of the integrated memory circuit device causes data from a page of the memory cells to be read and stored in the plurality of latches. Thereafter the contents of the plurality of latches are read, typically, in a serial manner, from the integrated memory circuit device. Programming of the integrated memory circuit device causes data from the external to be stored in the plurality of latches. Thereafter, the contents of the plurality of latches are stored in a page of non-volatile memory cells. Typically a page of non-volatile memory cells lie in the same row or word line.
In a conventional page-mode read operation, whenever a word line is addressed, a wait state is necessary for the on-chip control circuits to sense out data stored in the memory cells of that selected word line. After being sensed out, the data is latched into the plurality of page buffers before they are clocked out to the I/O pads. This wait-state, typically around several micro-seconds, accounts for a significant portion of the average page-mode read access time. Especially in applications of reading large volume data, several consecutive word lines are often addressed successively. With one wait-state for each addressed word line, the overall read performance is deteriorated. Therefore, a non-volatile memory with minimized number of wait-states is needed to provide high performance page-mode read operation.
In U.S. Pat. No. 5,768,215 a proposed solution to the aforementioned problem of the wait state is to provide two groups of page buffers, with each group of page buffers being one half the size of a page of memory cells. Initially, the data from a first page of memory cells is read into the two groups of page buffers. Thereafter, a first group of page buffers is read and the contents outputted to the external. However, as soon as the reading of the contents of the second group of page buffers commences, the reading of a second page of memory cells commences with the data read from one half of the second page of memory cells being stored in the first group of page buffers. After the contents of the second group of page buffers is outputted to the external, one half of the second page of memory cells will also have been read and stored in the first group of page buffers. As the reading of the first group of page buffers commences, the reading of the second half of the second page of memory cells commences and is stored in the second group of page buffers. This alternation of reading one half of a page of memory cells and storing the data into one of the groups of page buffers, while the contents of the other group of page buffers is read out continues.
In a conventional page-mode program operation, data is first loaded into the plurality of page buffers sequentially. Regardless of the number of bits (or collective bytes) to be programmed, all the data loaded into the plurality of page buffers will be programmed into the memory cells of a selected page simultaneously. Since the on-chip circuits, such as the charge pump (because typically programming requires a voltage source higher than the externally supplied voltage) can deliver only a limited amount of current, the efficiency of programming will deteriorate as the number of bits increases. Because of the limitation in the amount of current that can be provided by the on-board charge pump, one solution is to require a larger amount of time to program a page (or more) of data. Therefore a new technique is needed to provide high efficiency programming.
Finally, non-volatile memory cells used in NAND architecture are typically of the stack gate type, such as that disclosed in U.S. Pat. No. 5,768,215. Further, the non-volatile memory cells used in NOR architecture can be both the stack gate type or the split gate type such as that disclosed in U.S. Pat. No. 5,668,757, whose disclosure is incorporated by reference in its entirety.
SUMMARY OF THE INVENTION
In the present invention, an integrated circuit memory device has a page of memory cells arranged in a plurality of sub-pages of memory cells. The memory cells are electrically coupled to a plurality of word lines, and a plurality of bit lines. A plurality of sub-page buffers are electrically coupled to the plurality of bit lines for storing data read from the memory cells coupled to the plurality of bit lines. The device further has an I/O data buffer. Each sub-page comprises a plurality of non-adjacent bit lines with memory cells coupled thereto, with the bit lines of each of the sub-page interleaving bit lines of another sub-page. A read controller circuit is coupled to the plurality of sub-page buffers for initiating a read operation to read data from a first sub-page of memory cells to an associated first sub-page buffer, while simultaneously reading data from a second sub-page buffer to said I/O data buffer.
The present invention also relates to an integrated circuit memory device having a NOR architecture emulating the read and programming operations of a NAND integrated circuit memory device. Finally, the present invention relates to a read-modify-write circuit.


REFERENCES:
patent: 5740122 (1998-04-01), Toda et al.
patent: 5768215 (1998-06-01), Kwon et al.
patent: 5844858 (1998-12-01), Kyung
patent: 6249481 (2001-06-01), Toda et al.
patent: 6377507 (2002-04-01), Tsao

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