Integrated circuit memory device and structural layout thereof

Details Integrated circuit memory device and structural layout thereof Integrated circuit memory device and structural layout thereof

1991-05-03

1993-03-30

Jackson, Jr., Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Non-single crystal, or recrystallized, semiconductor...

Field effect device in non-single crystal, or...

257331, 257333, 257351, 257377, 257393, 257395, 257622, 257653, 257756, 257903, H01L 2702, H01L 2910, H01L 2906

Patent

active

051986833

ABSTRACT:
A memory cell layout achieves a reduced cell area. In one embodiment, a six transitor (6T) SRAM cell has two vertical thin-film transistors (18 and 20) as load transistors, two transfer transistors (10 and 12), two latch transistors (14 and 16), and two storage nodes. NODE 1 and NODE 2 of the cell each have a minimum feature defined by trenches (60). Four of five interconnects associated with each node are located within the respective trench. For example in NODE 1, a drain of latch transistor (14), a gate of latch transistor (16), a drain of load transistor (18), and a current electrode of transfer transistor (10) are electrically coupled within or beneath one trench (60). A remaining interconnection of NODE 1, a gate of load transistor 20, is located within the trench associated with NODE 2. Thus, ten interconnects of the memory cell are contained within areas defined by two minimum features.

REFERENCES:
patent: 5016070 (1991-05-01), Sundaresan
R. Eklund et al., "A 0.5 um BICMOS Technology For Logic and 4MBit-Class SRAMS's," IEDM Proceedings 1989, pp. 425-428.
T. E. Tang et al., "VLSI Local Interconnect Level Using Titanium Nitride," IEDM Proceedings 1985, pp. 590-593.

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