Integrated circuit logic with self compensating block delays

Details Integrated circuit logic with self compensating block delays Integrated circuit logic with self compensating block delays

2006-08-01

2006-08-01

Pham, Hoai (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

C257S501000

Reexamination Certificate

active

07084476

ABSTRACT:
An integrated circuit (IC) including at least one combinational logic path. The combinational logic path includes two types of logic blocks cells that compensate each other for fabrication parameter effects on cell transistors. The two types may be dense cells with field effect transistor (FET) gates on contacted pitch and isolated cells with FET gates on wider than contacted pitch. Dense cell delay changes from the FET gates being printed out of focus are offset by isolated cell delay changes.

REFERENCES:
patent: 5563012 (1996-10-01), Neisser
patent: 6871338 (2005-03-01), Yamauchi
patent: 2002/0030510 (2002-03-01), Kono et al.
patent: 2004/0208266 (2004-10-01), Lenosky
Orshansky et al., A General Proabalistic Framework for Worst Case Timing Analysis, DAC 2002, Jun. 10, 2002, pp. 556-561, Published in: New Orleans, LA.

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