Integrated circuit layout pattern for cross-coupled circuits

Details Integrated circuit layout pattern for cross-coupled circuits Integrated circuit layout pattern for cross-coupled circuits

2011-06-14

2011-06-14

Jackson, Jr., Jerome (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular signal path connections

C257SE27108

Reexamination Certificate

active

07960759

ABSTRACT:
A circuit32is provided comprising a first diffusion region34and a parallel second diffusion region36. A sequence of N gate layers40, 42, 46is provided with a first and an Nth of these gate layers covering different respective ones of the diffusion regions34, 36whilst the middle (N−2) gate layers42cover both diffusion regions34, 36. A bridging conductor64connects the first gate layer40and the Nth gate layer46. In some embodiments, the second diffusion region is provided as two second diffusion sub-regions68, 70having a diffusion region gap74therebetween and electrically connected via a jumper connector42. A first gate layer76which forms a gate electrode with a first diffusion region66can extend through this diffusion region gap74not forming a gate electrode therewith and facilitating use of a collinear bridging conductor82to connect to the Nth gate layer80.

REFERENCES:
patent: 5223733 (1993-06-01), Doi et al.
patent: 5684311 (1997-11-01), Shaw
patent: 6144241 (2000-11-01), Wong
patent: 6800883 (2004-10-01), Furuya et al.
patent: 7638822 (2009-12-01), de Jong et al.
patent: 2004/0089881 (2004-05-01), Ono
patent: 2008/0105904 (2008-05-01), Sumikawa et al.

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