Integrated circuit interlevel dielectric wherein the first and s

Details Integrated circuit interlevel dielectric wherein the first and s Integrated circuit interlevel dielectric wherein the first and s

1991-10-31

1993-10-12

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437225, 437228, H01L 2100, H01L 2102, H01L 21302, H01L 21463

Patent

active

052525201

ABSTRACT:
A method for forming a dielectric layer in an integrated circuit is disclosed. After a first dielectric layer is formed, a second dielectric layer is formed on top of the first layer. The second layer is formed by reducing precursor gas flow during the initial portion of the deposition process so that the initial film density of the deposited dielectric is higher or equal to the density of the bulk of the first and second dielectric.

REFERENCES:
patent: 4872947 (1989-10-01), Wang et al.
"Plasma TEOS Process for Interlayer Dielectric Applications," B. L. Chin et al., Solid State Technology, Apr. 1988, pp. 119-122.
"Reactive Facet Tapering of Plasma Oxide for Multilevel Interconnect Applications," T. Abraham, IEEE VLSI Multilevel Interconnection Conference, Jun. 15-16, 1987, 115-121.

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