Integrated circuit interface stage for high noise environment

Details Integrated circuit interface stage for high noise environment Integrated circuit interface stage for high noise environment

1975-03-26

1976-08-10

Larkins, William D.

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307213, 340 52E, 357 35, 357 44, 357 48, H01L 2704

Patent

active

039744043

ABSTRACT:
An interface circuit for integrated circuit devices which prevents deleterious injection of minority carriers into the substrate during overvoltages applied to a terminal of the integrated circuit. A lateral PNP transistor formed in an N-type region has its base connected to a bias circuit and its collector connected to a load circuit and its emitter connected to a current source having a P-type electrode. The emitter is also connected to a first terminal of the integrated circuit. If the first terminal is connected to a signal wire having large negative noise pulses thereon, the emitter-base junction of the lateral PNP transistor will become reverse biased during the negative pulses, thereby preventing the injection of minority carriers into the P-type substrate in which the integrated circuit is fabricated. If the terminal is connected to a second terminal of a second integrated circuit having therein a lateral PNP transistor having its base connected to a control circuit and its collector connected to a load circuit, the first and second lateral PNP transistors and the current source form a differential amplifier, which provides a low impedance to noise impulses applied to the terminals.

REFERENCES:
patent: 3411051 (1968-11-01), Kilby
patent: 3412460 (1968-11-01), Lin
patent: 3538449 (1970-11-01), Solomon
patent: 3622812 (1971-11-01), Crawford
Hibberd, Integrated Circuits (McGraw-Hill, NY, 1969), pp. 79-81.

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