Wave transmission lines and networks – Coupling networks – With impedance matching
Reexamination Certificate
2002-08-02
2003-11-11
Pascal, Robert (Department: 2817)
Wave transmission lines and networks
Coupling networks
With impedance matching
C333S247000, C333S260000, C257S664000, C257S773000
Reexamination Certificate
active
06646520
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a system for interconnecting multiple devices implemented in an integrated circuit (IC) to a circuit node external to the IC, and in particular to a system employing and distributing appropriately-sized inductors and capacitors to isolate and impedance match the IC devices to enhance interconnect system frequency response.
2. Description of Related Art
In an integrated circuit (IC), each signal transmitter or receiver device that communicates with a circuit node external to the IC is typically linked to a bond pad on the surface of the IC's substrate. In a typical packaged IC a bond wire connects the bond pad to a conductive leg or pin extending from the package surrounding the IC. When the IC package is mounted on a printed circuit board (PCB), the package leg is soldered to a microstrip trace on the surface of the PCB or to a conductive via passing through the PCB to a stripline conductor on another layer of the PCB. When bond pads of one or more other ICs mounted on the PCB are linked to the PCB trace in a similar manner, the bond pads, bond wires, package legs, and the PCB trace form an interconnect system for conveying signals between devices implemented in two or more ICs. Many ICs also include electrostatic discharge protection devices (ESDs) also connected to each bond pad to protect the IC from high voltage static discharges which can damage the device.
In high frequency applications a combination of series inductances and shunt capacitances in the signal path provided by the interconnect system attenuate and distort signals. The bond wire and package leg typically contribute most of the series inductance. The capacitance of any IC driver, receiver and/or ESD device connected to the bond pad and the capacitance of any device connected to the PCB trace (such as for example, a via) provide most of the interconnect system capacitance. The conventional approach to reducing the amount of signal distortion and attenuation caused by the interconnect system has been to minimize the series inductance and shunt capacitance of the interconnect system. The inductance of bond wires and package legs can be minimized by keeping them as small as possible. Driver, receiver and ESD capacitances can be controlled to some extent by controlling shapes and dimensions of structures within the IC. The PCB trace impedance can be controlled by appropriately choosing physical characteristics of the trace such as its width and length, its spacing from ground planes and dielectric nature of the insulating material forming the circuit board. Vias, conductors passing vertically through a circuit board to interconnect PCB traces on various layers of the PCB, can be a source of capacitance along the PCB trace. Designers avoid the use of vias in high frequency applications in order to limit the shunt capacitance of the interconnect system. When vias are unavoidable, designers typically structure them so as minimize their capacitance. Although minimizing the inductance of the bond wire and package leg, the capacitances of the trace, drivers, receivers and ESD devices can help increase the bandwidth, flatten frequency response and reduce the signal distortion, it is not possible to completely eliminate interconnect system inductance and capacitance. Thus some level of signal distortion and attenuation is inevitable when signal frequencies are sufficiently high.
What is needed is a way to substantially improve various characteristics of frequency response of the interconnect system beyond that which is attainable by reducing interconnect system inductances and capacitances to minimum attainable values.
SUMMARY OF THE INVENTION
An interconnect system in accordance with the invention provides a signal path between multiple devices such as drivers, receivers and electrostatic protection devices implemented on an integrated circuits (IC) and a single external circuit node such as a printed circuit board (PCB) trace.
In accordance with one aspect of the invention, each such device is connected to a separate contact on the IC. The separate contacts are interconnected to one another and to the trace by inductive conductors. The conductor inductance isolates the device capacitances from one another, thereby improving various characteristics of the frequency response of the interconnect system, for example, by increasing bandwidth and decreasing signal distortion.
In accordance with another aspect of the invention the inductive conductors are bond wires.
In accordance with a further aspect of the invention, in an alternative embodiment thereof, the inductive conductors are separate legs of a forked, lithographically-defined spring contact.
In accordance with a further aspect of the invention, in an alternative embodiment thereof, the inductive conductors include lithographically-defined traces formed on a metalization layer of the IC die.
In accordance with yet another aspect of the invention, capacitance is added to the PCB trace, suitably by an appropriately dimensioned via. The magnitude of the conductor inductances and of the added trace capacitance are appropriately adjusted to optimize characteristics of the interconnect system frequency response.
In accordance with a still further aspect of the invention, electrostatic protection is provided within an integrated circuit by a set of two or more shunt capacitive electrostatic discharge (ESD) devices linked by series inductors. The shunt capacitance of the ESD devices and the series inductance of the inductors are tuned so that the ESD devices and inductors act as a multi-pole, low-pass filter tuned to further optimize various characteristics of the frequency response of the interconnect system, for example, by increasing bandwidth and decreasing signal distortion.
It is accordingly an object of the invention to provide a system for interconnecting integrated circuits having an improved frequency response.
The concluding portion of this specification particularly points out and distinctly claims the subject matter of the present invention. However those skilled in the art will best understand both the organization and method of operation of the invention, together with further advantages and objects thereof, by reading the remaining portions of the specification in view of the accompanying drawing(s) wherein like reference characters refer to like elements.
REFERENCES:
patent: 5901022 (1999-05-01), Ker
patent: 6459343 (2002-10-01), Miller
patent: WO98/47190 (1998-10-01), None
FormFactor Inc.
Jones Stephen E.
Pascal Robert
Smith-Hill and Bedell PC
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