Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – With rotor
Patent
1990-01-16
1991-10-08
Karlsen, Ernest F.
Electricity: measuring and testing
Measuring, testing, or sensing electricity, per se
With rotor
324 731, 371 111, 371 221, G01R 3128
Patent
active
050557742
DESCRIPTION:
BRIEF SUMMARY
This invention relates to integrated circuits of the kind in which a multiplicity of semiconductor regions of a unitary substrate each contain a circuit that is adapted to store and/or process data and to transfer signals to, and to receive signals from, others of the circuits, a control condition is derived in dependence upon signal responses that occur within the individual circuits according to the integrity of circuitry within those circuits, and interconnections of the circuits with one another for the purposes of the transfer and reception of signals between the circuits are enabled or disabled in dependence upon the derived control condition.
Integrated circuits of this kind are known from UK Patent Specification No. 1,377,859. In UK Patent Specification No. 1,377,859 there is described an integrated circuit in which a multiplicity of regions of a unitary semiconductor wafer-substrate each contain a circuit that is adapted to store and/or process data and to transfer data signals to, and to receive data signals from, others of the circuits. In particular, the construction of a multi-stage shift register is described, each of the circuits incorporating two sections of shift register that are interconnected serially with the corresponding sections of a multiplicity of other circuits on the wafer, in order to make up the complete, extended shift-register. The provision of the shift register in this way involves the progressive building up of a chain of the circuits connected in cascade with one another, each circuit being added in turn to extend the chain only following testing of the integrity of that circuit to make sure that it is not faulty. The testing is carried out in each case from an external unit that checks that digital words entered into the circuit via such of the chain as is already established, are returned from that circuit via the chain, without error. If there is error, the circuit under test is rejected by disabling the connection of that circuit in the chain, and the process of selection and testing repeated towards identifying another circuit for which there is no error. Once a no-error response has been achieved from a tested circuit, that circuit is added to extend the chain, and selection of another circuit for testing is made; provided this other circuit fulfills the requirement for circuit-integrity, it too is added to extend the chain further, and so on until the complete shift-register is built up.
Integrated circuits constructed and operated according to the technique disclosed in UK Patent Specification No. 1,377,859, have been found advantageous in practice. However, they have the disadvantages that the external circuit required to select and test the circuits, is generally complex and entails significant costs (possibly comparable with those involved in the provision of the wafer circuit itself), and the selection and testing process, in which each circuit is selected and tested in turn, takes significant time.
It is an object of the present invention to provide an integrated circuit of the kind specified that enables the above disadvantages to be overcome, or at least reduced.
According to the present invention there is provided an integrated circuit of the kind specified, characterised in that each said region, or at least each of a plurality of groups of said regions, includes logic circuitry individual to the respective region or group of regions for determining circuit integrity within that region or group and deriving said control condition, and that the said logic circuitry in each region or group acts to check the circuit integrity of that individual region or group, and thereby derive said control condition, according to a plurality of successive testing steps that involve progressively larger portions of the region or group and begin from at least a section of the logic circuitry without test of its integrity.
Thus, according to the present invention the individual component circuits, or the groups of such circuits, test themselves, rather than depending wholly
REFERENCES:
patent: 4038648 (1977-07-01), Chesley
patent: 4254477 (1981-03-01), Hsia et al.
patent: 4398248 (1983-08-01), Hsia et al.
patent: 4868789 (1989-09-01), MacDonald
Proceedings of the IEEE International Conference on Computer Design: VSLI in Computers, 6-9 Oct. 1986; Port Chester, New York, IEEE, (New York, U.S.), V. K. Agarwal et al.: "Techniques for Implementing Large Area Devices", pp. 220-224 See P. 220, Left-Hand Column, Line 46-Right-Hand Column, Line 2; p. 222, Left-Hand Column, Line 29-Right-Hand Column, Line 60.
Systems Technology, No. 31, Apr. 1979, (Liverpool, GB), G. Edge: "Fault Diagnosis in Computer Control Systems":, pp. 33-41 See P. 35, Left-Hand Column, Lines 51-61.
Proceedings of the 8th Annual Symposium on Computer Architecture, 12-14 May 1981, Minneapolis, Minnesota, IEEE.
IEEE Proceedings-E/Computers Digital Techniques 134 (1987) Mar., 2, Part E Stebenage Herts, Great Britain "Techniques for Implementing Two Dimensional Wafer-Scale Processors or Rays", Jesshope et al.
IEEE Journal of Solid-State Circuits, vol. SC-15, No. 3 Jun. 1980 "Built-In Test for Complex Digital Integrated Circuits", Konemann, et al.
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