Active solid-state devices (e.g. – transistors – solid-state diode – With means to control surface effects – Insulating coating
Reexamination Certificate
1997-04-25
2001-08-21
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
With means to control surface effects
Insulating coating
C257S524000, C438S623000
Reexamination Certificate
active
06278174
ABSTRACT:
The invention relates to semiconductor devices, and, more particularly, to integrated circuit insulation and methods of fabrication.
Integrated circuits typically include field effect transistors with source/drains formed in a silicon substrate and insulated gates on the substrate together with multiple overlying metal (or polysilicon) interconnections formed in levels. An insulating layer lies between the gates/sources/drains and the interconnections formed from the first metal level (premetal dielectric) and also between successive metal levels (intermetal-level dielectric). Vertical vias in the insulating layers filled with metal (or polysilicon) provide connections between interconnections formed in adjacent metal levels and also between the gate/source/drain and the first metal level interconnections. Each insulating layer must cover the relatively bumpy topography of the interconnections of a metal level or the gates, and this includes crevices between closely spaced interconnects in the same metal level. Also, the dielectric constant of the insulating layer should be as low as practical to limit capacitive coupling between closely spaced interconnects in the same metal level and in adjacent overlying and underlying metal levels.
Various approaches form silicon dioxide (oxide) insulating layers over bumpy topography: reflowing deposited borophosphosilicate glass (BPSG), using spin-on glass (SOG), sputtering while depositing in plasma enhanced chemical vapor deposition (PECVD) with tetraethoxysilane (TEOS) plus oxygen as source gasses, etching back a stack of deposited glass plus spun-on planarizing photoresist, and chemical-mechanical polishing (CMP) deposited oxide.
All these oxide approaches have problems including the relatively high dielectric constant of silicon oxides: roughly 3.9-4.2. This limits how closely the interconnections can be packed and still maintain a low capacitive coupling.
Laxinan, Low ∈Dielectrics: CVD Fluorinated Silicon Dioxides, 18 Semiconductor International 71 (May 1995), summarizes reports of fluorinated silicon dioxide for use as an intermetal level dielectric which has a dielectric constant lower than that of silicon dioxide. In particular, PECVD using silicon temfluoride (SiF
4
), silane (SiH
4
), and oxygen (O
2
) source gasses can deposit SiO
x
F
y
with up to 10% fluorine and a dielectric constant in the range 3.0 to 3.7. But this dielectric constant still limits the packing density of interconnections. Alternatives sandwich the fluorinated oxide between layers of conformally deposited silicon dioxide.
Organic polymer insulators provide another approach to low dielectric constant insulators. Formation by vapor deposition ensures filling of crevices between closely spaced interconnections. For example, parylenes are thermoplastic polymers that have low dielectric conslnts (e.g., 2.35 to 3.15), low water affinity, and may be conformally deposited from a vapor without solvents and high temperature cures. Parylene with hydrogen on the aliphatic carbons may be used at temperatures up to about 400° C. under an N
2
atmosphere, whereas aliphatic perfluorination increases the useful temperature to about 530° C. However, these conformal depositions must be planarized, and typically the polymer is etched back and a planaing silicon oxide deposition is applied over the polymer.
Lastly, a sort of hybrid of polymers and spin-on-glasses, hydrogen silsesquioxane (HSQ), may be spun-on and cured to yield an insulator with dielectric constant about 3.0. Indeed, first deposit a conformal coat of silicon oxide (such as PECVD of TEOS) over bumpy topography, then spin on HSQ to fill in the gaps for planarity, cure the HSQ, and finally deposit a cap layer of oxide. The HSQ has good gap filing capabilities but can potentially crack for thick films, e.g., roughly 1 &mgr;m. Thus the cap layer of oxide may be relatively thick. However, the HSQ/cap oxide structure has an effective dielectric constant much higher than tat of pure HSQ, and some of the benefit of the HSQ is lost.
SUMMARY OF THE INVENTION
The present invention provides an intermetal level dielectric or premetal level dielectric structure with two (or more) low dielectric constant insulating materials: one material for gap filling and the other material for filling up to an overlying metal level.
Preferred embodiments use gap filling with spin on materials such as HSQ together with level filling materials such as PECVD fluorinated oxide.
Advantages include an insulating structure having a low effective dielectric constant which makes use of a good gapfilling low-dielectric-constant material having limitations such as cracking of thick layers.
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Gutmann et al., “Low Dielectric Constant Polymers for On-Chip Interlevel Dielectrics with Copper Metalization”, Mat. Res. Soc. Symp. Proc., vol. 381, pp. 177-195, Apr. 17, 1995.*
Laxman, Ravi K., “Low E Dielectrics: CVD Fluorinated Silicon Dioxides”, Semiconductor International, vol. 18, pp. 71-74, May 1995.*
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Havemann Robert H.
Jain Manoj K.
Brady III Wade James
Chaudhuri Olik
Hoel Calton H.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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