Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
1997-06-09
2001-11-06
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S424000, C438S437000, C148SDIG005
Reexamination Certificate
active
06313010
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to semiconductor devices, and, more particularly, to integrated circuit insulation and methods of fabrication.
Integrated circuits typically include field effect transistors with source/drains formed in a silicon substrate and with insulated gates on the substrate plus multiple overlying metal (or polysilicon) wiring levels with an insulating layer between the gates/sources/drains and the first metal level wiring and between successive metal level wirings. Vertical vias in the insulating layers filled with metal (or polysilicon) provide connections between adjacent metal level wirings and between the gate/source/drain and the first metal level wiring. Further, the transistors are isolated from one another on the substrate by insulation areas formed by oxidation. This local oxidation of the silicon (LOCOS) substrate for device isolation has problems including the “bird's beak” lateral encroachment into device areas by the isolating oxide during its growth. This lateral encroachment occupies intolerably large fractions of the available silicon substrate area as the transistor size decreases.
Shallow trench isolation for integrated circuits with linewidths of 0.25-0.35 &mgr;m has been proposed as a solution to the bird's beak encroachment problem of LOCOS isolation. In particular, Gosho et al, Trench Isolation Technology for 0.35 &mgr;m Devices by Bias ECR CVD, 1991 VLSI Symp Tech Digest 87, describes a process which first etches trenches in a substrate and then fills the trenches with oxide by electron cyclotron resonance (ECR) plasma enhanced oxide deposition. The deposition uses a gas mixture of silane (SiH
4
) and nitrous oxide (N
2
O) and begins with the silane to nitrous oxide ratio set to deposit oxide faster than it is sputtered off for surfaces tilted less than 30 or more than 60 degrees from the direction of ion bombardment from the plasma. Once the trenches are filled (and large areas between the trenches have accumulated thick oxide deposits), then the silane to nitrous oxide ratio is adjusted to deposit oxide faster than it is sputtered off for surfaces tilted about 0 or more than 80 degrees from the direction of ion bombardment. This second step of plasma deposition basically contracts the oxide deposits on the areas between the trenches. The photolithographically mask off the trenches and closely adjacent areas; this exposes the oxide deposits on the areas between the trenches. Lastly, strip these exposed oxide deposits to leave oxide filled trenches. See
FIGS. 3
a-f
illustrating this process and
FIG. 4
showing the sputter etch rate and deposition rate depending upon surface tilt for two different gas mixtures.
Alternative trench isolation schemes include filling the trenches with spin on glasses such as hydrogen silsesquioxane (HSQ) or chemical vapor deposition using ozone plus tetrathoxysilane (TEOS).
These approaches have problems including thermal annealing for the HSQ and TESO and complex planarization and possible ECR damage to trench edges.
SUMMARY OF THE INVENTION
The present invention provides a trench isolation scheme using an inductively coupled high density plasma enhanced deposition of oxide for trench filling along with chemical mechanical polishing of the deposited oxide using part of the trench etch mask as the polish stopping layer.
This deposition method has the advantages including simple processing and avoidance of plasma ion bombardment damage.
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Dishing Effects in a Chemical Mechanical Polishing Planarization Process for Advanced Trench Isolation; C. Yu et al.; Appl. Phys. Lett., vol. 61, No. 11, Sep. 14, 1992; pp. 1344-1346.
Chatterjee Amitava
Chen Ih-Chin
Nag Somnath S.
Brady W. James
Dang Trung
Hoel Carlton H.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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