Integrated circuit input/output processor having improved timer

Details Integrated circuit input/output processor having improved timer Integrated circuit input/output processor having improved timer

1995-11-13

1997-05-27

Heckler, Thomas M.

395306, G06F 1340, G06F 104

Patent

active

056340451

ABSTRACT:
Referring to FIGS. 1 and 2, I/O control modules (IOCMs 25-29) have channels which communicate by way of timer buses (71, 72) and pin/status buses (75-77). Channels (86, 87) are partitioned by each timer bus (71, 72) into separate blocks of channels (86, 87) which are provided with access to different timebase values from timebase channels (80, 81) by their respective timer bus (71, 72), so there is no loss of resolution because each channel in a timer bus block (e.g. 86) can concurrently receive the same timebase value from its corresponding timer bus (71). Pin/status buses (75-77) allow simultaneity of control among the channels (e.g. 58) coupled to the same pin/status bus (e.g. 76). Pin/status buses (75-77) and timer buses (71, 72) can be independently partitioned.

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