Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
1999-05-03
2001-10-30
Meler, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
Reexamination Certificate
active
06310387
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit inductors and more particularly to integrated circuit inductors having a high self-resonance frequency and a high quality factor, Q
n
.
2. Description of Related Art
It is desirable to include inductors on integrated circuits (“IC”) versus off the IC to reduce the form factor and cost of devices requiring inductors. IC inductors, however, commonly have unacceptably low quality factors, low self-resonance, and cause interference with surrounding or neighboring IC components. This is particularly true for IC inductors used in high frequency applications such as in the front end of radio frequency (“RF”) receivers and transmitters.
Due to the significant advantages of having IC inductors, several solutions have been investigated. First, inductors having different geometric patterns such as those shown in
FIGS. 1A
to
1
C have been analyzed including a spiral inductor
42
, a simple loop inductor
44
, and a meander inductor
46
. Of these inductors, investigation has revealed that spiral inductors are most easily adapted for inclusion in silicon ICs because a desired inductance can be achieved using a smaller surface area with a spiral inductor versus a loop or a meander inductor.
As way of background
FIG. 2A
shows such an inductor
50
which generates magnetic field lines
52
due to the flow of current shown in the FIGURE.
FIG. 2B
illustrates a cross sectional view of an IC structure
54
including the inductor
50
. The IC
54
includes a silicon substrate
56
, a conductive ground plane
58
, and a silicon oxide layer
60
. When the inductor
50
is included on an IC such as shown in FIG.
2
B and current flows through the inductor
50
such as shown in
FIG. 2A
, the lines of magnetic field can enter the substrate
56
and be significantly reduced. This reduces the quality factor (Q
n
) of the inductor. In addition the frequency at which the inductor
50
self-resonances is also reduced due to parasitic capacitance between the inductor
50
and the substrate
56
.
In order to limit the passage of the magnetic fields of an inductor into the IC's substrate, insulating regions and ground plates have been inserted between the inductor and substrate. For example, U.S. Pat. No. 5,539,241 to Abidi et al. teaches etching a pit under the inductor to create an insulating region between the inductor and the substrate. As noted in the PCT application number US98/05149 to Yue et al. (which is discussed below), the inclusion of this insulating region may effect the mechanical integrity of the IC, in particular, the inductor. In addition, the construction of an IC with such insulating region is likely to be expensive and complex.
Yue et al. also discusses another IC inductor structure where the structure includes a solid metal conducting ground shield
72
such as shown in FIG.
3
A. As shown in
FIG. 3B
, the solid conducting ground shield
72
is placed between the inductor
50
and the substrate
56
. As shown in
FIG. 3A
, an image current
76
is induced from the magnetic field lines generated by the inductor
50
. This induced image current
76
generates magnetic field lines
74
where the flux of the magnetic field is opposite the flux of the magnetic field of the inductor
50
. Consequently, while this IC inductor configuration isolates the inductor
50
from the substrate
56
(no magnetic coupling), the configuration substantially reduces the effective inductance of the inductor and thereby the Q
n
of the inductor. In order to overcome these problems, Yue et al. suggests an IC inductor configuration that includes a patterned ground shield
80
between the inductor
50
and substrate
56
as shown in
FIGS. 4A and 4B
. The patterned ground is a polysilicon ground shield that includes locally isolated conductive lines
84
separated by slots
85
where the conductive lines
84
are orthogonal to the conductive line segments of the inductor
50
. Yue et al. teaches that the orthogonal relationship between the conductive lines
84
and conductive line segments reduces or eliminates the generation of an image current in the ground shield
80
. The ground shield effectively terminates any electric field generated by the inductor
50
thus limiting any leakage into the substrate
56
. The termination of the electric field at the ground shield
80
, however, may effectively generate a quasi capacitor where the inductor acts as one plate and the ground shield acts as another plate. The relative proximity of the inductor to the ground shield increases its effective capacitance. Consequently, the IC inductor configuration of Yue et al. may not have an acceptable quality factor at high frequencies.
It is also noted that Yue et al. suggests that the substrate
56
is a low resistivity substrate. In particular, Yue et al. includes examples of an 11 ohm-cm silicon substrate and a 19 ohm-cm silicon substrate. It has been found that low resistivity substrates employed in IC inductor configurations may also lower the self-resonance frequency of the inductor regardless of the ground shield or grounding technique employed. Thus, a need exists for an IC inductor configuration that has a high self-resonance frequency and an acceptable quality factor at high frequencies.
SUMMARY OF THE INVENTION
The present invention is an integrated circuit inductor structure that includes a shielding pattern that induces a plurality of small eddy currents to shield magnetic energy generated by the inductor from the substrate of the IC. The IC inductor structure is formed on a Silicon on Insulator (SOI) substrate where the substrate of the SOI has high resistivity. The shielding pattern forms a checkerboard pattern that includes a plurality of conducting regions completely isolated from each other by a dielectric or non-conducting material. The inductor has a high quality factor and a high self-resonance frequency due to the effective shielding of electromagnetic energy from the substrate of the IC while not reducing the effective inductance of the inductor or introducing substantial parasitic capacitance.
In other embodiment, the IC inductor structure includes an inductor formed over a second dielectric layer. The second dielectric layer is formed over a first dielectric layer and the first dielectric layer is formed over a substrate. The substrate ideally has high resistivity. In particular, the resistivity is about 1 kohm-cm. The first dielectric layer is formed from silicon oxide and the second dielectric layer is formed from at least one oxide layer. In another embodiment, a plurality of conducting regions are inserted into the second dielectric layer wherein the plurality of conducting regions induce small eddy currents that do not significantly reduce the inductance of the inductor.
REFERENCES:
patent: 5070317 (1991-12-01), Bhagat
patent: 5431987 (1995-07-01), Ikeda
patent: 5539241 (1996-07-01), Abidi
patent: 5694030 (1997-12-01), Sato et al.
patent: 5747870 (1998-05-01), Peddler
patent: 5884990 (1999-03-01), Burghartz et al.
patent: 6160303 (2000-12-01), Fattaruso
patent: 9-132498 (1997-05-01), None
patent: 98/05149 (1998-03-01), None
Muller et al,Device Electronics for IC's, pp 63-65, 1986.*
Ronkainen, et al., “IC Compatible Planar Inductors on Silicon”, IEEE Proceedings: Circuits Devices and Systems, GB, Institution of Electrical Engineers, Stenvenage, vol. 144, No. 1, Feb. 1, 1997, pp. 29-35.
Hull Christopher D.
Seefeldt James Douglas
Jaquez & Associates
Jaquez, Esq. Martin J.
Meler Stephen D.
Silicon Wave Inc.
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