Integrated circuit incorporating a test circuit

Details Integrated circuit incorporating a test circuit Integrated circuit incorporating a test circuit

1996-05-08

1997-09-23

Canney, Vincent P.

Excavating

G06F 1100

Patent

active

056712332

ABSTRACT:
Disposed in an integrated circuit is a test circuit having: a plurality of tristate buffers each for supplying, in a test mode, a charging current to a stray capacitance of a corresponding wire on a printed circuit board through a corresponding signal terminal of the integrated circuit; and a plurality of exclusive-OR gates each for supplying a logical signal having a pulse width indicative of a time interval between an input transition time and an output transition time of a corresponding tristate buffer. A difference in capacitance between a state where a signal terminal is being properly electrically connected to a wire on the printed circuit board and a state where the signal terminal is being improperly electrically connected thereto, is converted into a difference in pulse width of a logical signal, based on which a defective soldering of open failure in the signal terminal is detected.

REFERENCES:
patent: 5084874 (1992-01-01), Whetsel, Jr.
patent: 5498964 (1996-03-01), Kerschner et al.
patent: 5557209 (1996-09-01), Crook et al.

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