Integrated circuit including fully testable small scale read onl

Details Integrated circuit including fully testable small scale read onl Integrated circuit including fully testable small scale read onl

1996-08-21

1997-12-02

Elmore, Reba I.

Boots, shoes, and leggings

348407, 348409, 348412, 348415, 371 225, 371 226, G06F 1714, H04N 712, H04N 1102, H04N 1104

Patent

active

056943466

ABSTRACT:
Disclosed is an integrated microprocessor chip. The chip includes a digital video decoder Inverse Discrete Cosine Transform element and an on chip Read Only Memory. The on chip Read Only Memory includes (a) a shift register latch for receiving data from off chip pull-up resistors, (b) a register for storing data, (c) a selector and a decoder for selecting memory cells to be read from the register, and (d) a Read Only Memory data output.

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IBM TDB, vol. 34, No. 7A, Dec. 1991; "Level-Sensitive Scan Design Latch-Trigger Implementation Of Microprocessor Architecture".
IBM TDM, vol. 25, No. 3A, Aug. 1982; "Partitioning Microcode For A Microprocessor-Based Mainframe By . . . ".
IBM TDB, vol. 21, No. 1, Jun. 1978; "Dynamic Random-Access Memory With Read-Only Memory Characteristics At Power-On Time".

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