Integrated circuit including ESD circuits for a multi-chip...

Details Integrated circuit including ESD circuits for a multi-chip... Integrated circuit including ESD circuits for a multi-chip...

2000-08-31

2003-04-29

Berhane, Adolf Deneke (Department: 2838)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Transient responsive

C361S056000

Reexamination Certificate

active

06556409

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to integrated circuits and, more particularly, to electrostatic discharge protection for multi-chip modules.
BACKGROUND OF THE INVENTION
For many years the trend in semiconductor device and package design has been toward ever-higher levels of integration, which in memory technology takes the form of integrating memory and logic on the same chip. Power modules and driver circuits are conventionally part of DRAM and SRAM devices, and many memory device designs have application specific logic embedded with the memory arrays on a common chip. However, while logic and memory semiconductor elements share many common features, there are differences. For example, a critical feature of a DRAM memory element is the storage capacitor. This element is made optimally small, and essentially without defects or leakage. Logic devices have no comparable element, and are more forgiving in many device aspects. Consequently, a wafer fabrication process that is tailored for memory device optimization is not usually optimum for logic devices. Thus, compromises are made in order to have different device species on the same semiconductor chip.
An alternative development to “integration or embedding” is the concept of “disintegration”, where memory devices consist mainly of memory cells and their necessary support circuits are kept in one chip while the “application” logic and other transistors are put on another chip. These chips can be processed optimally for the size and nature of their components. In this technology, the “integration” is performed at the package level, and the key to its success is a packaging technology that produces a final product that is superior to a chip integrated system in performance and cost, and at least comparable in size. A leading candidate for this packaging technology is flip chip bonding and assembly. Flip chip bonding is a well developed technology and is characterized by bonding a bare silicon IC die upside down on an interconnect substrate such as a printed wiring board. Several bonding techniques have been developed, e.g. ball bonding, ball grid array (BGA—a form of ball bonding), and solder bump bonding. These techniques lead to relaxed I/O pitch through smaller contact surfaces, and area arrays rather than perimeter arrays for chip interconnection sites. Moreover, electrical performance is enhanced because lead lengths are reduced. Typically, the bonding method in these techniques is solder bonding.
A recent advance in multi-chip module technology is the chip-on-chip approach where an active chip is flip-chip bonded to another active chip rather than to an interconnection substrate. When the relative sizes of the chips allow, two or more small chips can be bonded to a larger chip. Logic chips, e.g. digital signal processors, are quite large with a footprint sufficient to contain at least two standard memory chips. The logic chip, i.e. the support chip, is packaged in a lead frame package thus eliminating the board or interconnection substrate of more conventional MCM packages. The intra chip interconnection circuitry in the chip-on-chip package is typically constructed on the surface of the support chip. During assembly of these packages, a need exists to protect the I/Os of the integrated circuits formed on the chips from electrostatic discharge.
The protection of integrated circuits from electrostatic discharge (ESD) has been a significant design issue, especially as transistor electrode dimensions continue to shrink. An excessively high ESD voltage conducted from a package terminal to the integrated circuit bond pad can easily damage input or output circuitry, unless protection techniques are adopted. It appears that the use of the lightly-doped drain (LDD) structures and silicided source/drain regions in integrated circuits has also increased ESD susceptibility, especially in output buffers that utilize n-channel field effect transistors. One study by C. Duvvuryand C. Diaz, “Dynamic Gate Coupling of NMOS for Efficient Output ESD Protection” Proceedings of the IRPS (1992), indicates that improved ESD performance can be obtained using a field oxide capacitor to couple the gate of the output transistor to the bond pad. In that technique, the output transistor is made to carry the ESD current. However, the field oxide capacitor undesirably increases the capacitive load on the bond-pad, requiring a larger output transistor.
A somewhat similar prior-art technique is shown in
FIG. 6
, where an output buffer
610
is connected to the bond pad
611
. A protective n-channel transistor
613
is connected to the bond pad for conducting ESD current (I) to the power supply conductor (VSS). The ESD charge is conducted to the gate of transistor
613
by capacitor
612
, typically about 10 picofarads in one design. This MOS initiated conduction allows transistor
613
to conduct by means of bipolar action during an ESD event, allowing the current I to flow. The resistor
614
, typically about 2 kilohms, causes the positive charge on the gate of transistor
613
to be conducted to VSS, thereby turning transistor
613
off after the ESD event has dissipated. In this manner, transistor
613
does not conduct during normal operation of the output buffer. However, the circuitry of
FIG. 6
requires that the protective transistor be sufficiently large so as to be able to carry the relatively large ESD current. This requirement increases the area to implement the output buffer. In addition, the transistor
613
presents an additional capacitive load to the buffer
610
, which again undesirably requires that the buffer has additional drive capability, and hence increased size.
There are numerous alternatives for providing ESD protection. However, many of these techniques provide unsatisfactory results when used for I/O buffers. In addition, these techniques do not address ESD in the multi-chip module environment. Therefore, there is a need for an ESD protection technique that mitigates certain problems associated with the prior techniques.
SUMMARY OF THE INVENTION
The present invention is directed to an integrated circuit that includes I/O circuitry that may or may not be protected from ESD damage. The protection from ESD damage may be selectively deactivated or activated or may not be present at all in one or more of the I/O circuits. In use, the integrated circuit may be coupled to another integrated circuit to form a multi-chip module where the ESD protection for the I/O circuitry between the modules is deactivated or not present. This is advantageous because the likelihood of ESD damage to this I/O circuitry is reduced once the multi-chip module is formed. It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.


REFERENCES:
patent: 5818086 (1998-10-01), Lin et al.
patent: 5969929 (1999-10-01), Kleveland et al.

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