Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2011-08-02
2011-08-02
Luu, Pho M (Department: 2824)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S230020, C365S233160, C365S238500, C365S238500
Reexamination Certificate
active
07990798
ABSTRACT:
An integrated circuit including a memory module having a plurality of memory banks is disclosed. One embodiment provides an even number of at least four memory banks. Each memory bank has a plurality of memory cells. Each two of the memory bank form a memory bank region and being alternately connected to an m-bit data bus. The memory banks are classified into two groups, each group including a memory bank of each memory bank region. The memory module further includes a selection device connected to the memory banks and being responsive to selection bits. The selection device selects one of the two groups of memory banks and a group of i memory cells within the memory banks of the selected group of memory banks to access the selected i memory cells per one stroke via the associated m-bit data buses of the memory groups including the selected memory banks, m being equal to an integer multiple of i.
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patent: 6396766 (2002-05-01), Lee
patent: 2005/0024975 (2005-02-01), Gratrex et al.
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patent: 2006/0250881 (2006-11-01), Kandolf et al.
patent: 2008/0002478 (2008-01-01), Park
Minzoni Alessandro
Obermaier Werner
Bui Tha-O
Dicke Billig & Czaja, PLLC
Luu Pho M
Qimonda AG
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