Patent
1986-08-11
1989-02-21
Carroll, J.
357 15, 357 231, 357 67, H01L 2948, H01L 2978, H01L 2702, H01L 2348
Patent
active
048070106
ABSTRACT:
An integrated circuit in complementary circuit technology comprising a substrate bias voltage generator which applies a negative (positive) substrate bias voltage to the p(n) substrate in which n(p) tubs are inserted. The source regions of the n(p)-channel FETs arranged in the substrate lie at ground potential. In order to avoid "latch-up" effects, an output of the substrate bias voltage generator is connected via a Schottky diode to a circuit point that lies at ground potential.
REFERENCES:
patent: 4233672 (1980-11-01), Suzuki et al.
patent: 4255677 (1981-03-01), Boonstra et al.
patent: 4300152 (1981-11-01), Lepselter
patent: 4408304 (1983-10-01), Nishizawa et al.
patent: 4513309 (1985-04-01), Cricchi
F. Mohammadi, "Silicides for Interconnection Technology," Solid State Technology, (Jan. 1981), pp. 65-72.
Takacs Dezso
Winnerl Josef
Carroll J.
Siemens Aktiengesellschaft
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