Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Patent
1992-03-05
1995-12-05
Nguyen, Viet Q.
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
365190, 365191, 365198, 327379, 327391, 327437, H03K 19003
Patent
active
054735750
ABSTRACT:
The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices.
The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and also bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an AddressValid bus line carry address, data and control information for memory addresses up to 40 bits wide.
REFERENCES:
patent: 3740723 (1973-06-01), Beausoleil et al.
patent: 3758761 (1973-09-01), Hanrion
patent: 3771145 (1973-11-01), Wiener
patent: 3821715 (1974-06-01), Hoff, Jr. et al.
patent: 3882470 (1975-05-01), Hunter
patent: 3924241 (1975-12-01), Kronies
patent: 3969706 (1976-07-01), Proebsting et al.
patent: 3972028 (1976-07-01), Weber et al.
patent: 3975714 (1976-08-01), Weber et al.
patent: 3983537 (1976-09-01), Parsons et al.
patent: 4007452 (1977-02-01), Hoff, Jr.
patent: 4038648 (1977-07-01), Chesley
patent: 4099231 (1978-07-01), Kotok et al.
patent: 4191996 (1980-03-01), Chesley
patent: 4205373 (1980-05-01), Shah
patent: 4247817 (1981-01-01), Heller
patent: 4249247 (1981-02-01), Patel
patent: 4286321 (1981-08-01), Baker et al.
patent: 4306298 (1981-12-01), McElroy
patent: 4315308 (1982-02-01), Jackson
patent: 4333142 (1982-06-01), Chesley
patent: 4355376 (1982-10-01), Gould
patent: 4373183 (1983-02-01), Means et al.
patent: 4385350 (1983-05-01), Hansen et al.
patent: 4443864 (1984-04-01), McElroy
patent: 4449207 (1984-05-01), Kung et al.
patent: 4468738 (1984-08-01), Hansen et al.
patent: 4470114 (1984-09-01), Gerhold
patent: 4481625 (1984-11-01), Roberts et al.
patent: 4488218 (1984-12-01), Grimes
patent: 4500905 (1985-02-01), Shibata
patent: 4519034 (1985-05-01), Smith et al.
patent: 4584672 (1986-04-01), Schutz et al.
patent: 4595923 (1986-06-01), McFarland, Jr.
patent: 4630193 (1986-12-01), Kris
patent: 4646270 (1987-02-01), Voss
patent: 4649511 (1987-03-01), Gdula
patent: 4649516 (1987-03-01), Chung et al.
patent: 4654655 (1987-03-01), Kowalski
patent: 4706166 (1987-11-01), Go
patent: 4719627 (1988-01-01), Peterson et al.
patent: 4745548 (1988-05-01), Blahut
patent: 4764846 (1988-08-01), Go
patent: 4770640 (1988-09-01), Walter
patent: 4779089 (1988-10-01), Theus
patent: 4785394 (1988-11-01), Fischer
patent: 4811202 (1989-03-01), Schabowski
patent: 4818985 (1989-04-01), Ikeda
patent: 4837682 (1989-06-01), Culler
patent: 4860198 (1989-08-01), Takenaka
patent: 4933835 (1990-06-01), Sachs et al.
patent: 4975763 (1990-12-01), Baudouin et al.
patent: 5023488 (1991-06-01), Gunning
patent: 5150325 (1992-09-01), Yanagisawa et al.
patent: 5198995 (1993-03-01), Dennard et al.
patent: 5254883 (1993-10-01), Horowitz et al.
patent: 5257232 (1993-10-01), Dhong, et al.
patent: 5266848 (1993-11-01), Nakagome et al.
Hawley, David, "Superfast Bus Supports Sophisticated Transactions," High Performance Systems (Sep. 1989).
International Search Report Dated Jul. 8, 1991 for PCT Patent Application No. PCT/US91/02590 filed Apr. 16, 1991.
T. Yang, M. Horowitz, B. Wooley, "A 4-ns 4K .times.1-bit Two-Port BiCMOS SRAM," IEEE Journal of Solid-State Circuits, vol. 23, No. 5, pp. 1030-1040 (Oct. 1988).
"Burndy Connects" Advertisement, Electronic Engineering Times, pp. T24-T25 (Feb. 24, 1986).
J. Frisone, "A Classificaion for Serial Loop Data Communications Systems, " Raleigh Patent Operations (Nov. 2, 1972).
A. Kahn, "What's the Best Way to Minimize Memory Traffic," High Performance Systems, pp. 59-67 (Sep. 1989).
N. Margulis, "Single Chip RISC CPU Eases System Design," High Performance Systems, pp. 34-36, 40-41, 44 (Sep. 1989).
R. Matick, "Comparison of Memory Chip Organizations vs. Reliability in Virtual Memories," FTCS 12th Annual International Symposium Fault-Tolerant Computing, IEEE Computer Society Fault-Tolerant Technical Committee, pp. 223-227 (Jun. 22, 1982).
U.S. Patent Application Ser. No. 444,643, filed Dec. 1, 1989, of Farmwald.
Agarwal et al., "Scaleable Director Schemes for Cache Consistency," 15th Intern. Symp. Comp. Architecture, pp. 280-289 (Jun. 1988).
Agarwal et al., "An Analytic Cache Model, " ACM Trans. on Comp. Sys., vol. 7(2), pp. 184-215 (May 1989).
Beresford, "How to Tame High Speed Design," High Performance Systems, pp. 78-83 (Sep. 1989).
Carson, "Advance On-Focal Plane Signal Processing for Nonplanar Infrared Mosaics," SPIE, vol. 311, pp. 53-58 (1981).
Chesley, "Virtual Memory Integration," Submitted to IEETC (Sep. 1983).
Davidson, "Electrical Design of A High Speed Computer Package," IBM J. Res. Develop., vol. 26, No. 3, pp. 349-361 (1982).
Hart, "Multiple Chips Speed CPU Subsystems,"High Performance Systems, pp. 46-55 (Sep. 1989).
Horowitz et al., "MIPS-X: A 20-MIPS Peak, 32-bit Microprocessor with On-Chip Cache," IEEE J. Solid State Circuits, vol. SC-22, No. 5, pp. 790-798 (Oct. 1987).
Kwon et al., "Memory Chip Organizations for Improved Reliability in Virtual Memories," IBM Technical Disclosure Bulletin, vol. 25, No. 6, pp. 2952-2957 (Nov. 1982).
Pease et al., "Physical Limits to the Useful Packaging Density of Electronic Systems," (Sep. 1988).
Peterson, "System-Level Concerns Set Performance Gains," High Performance Systems, pp. 71-77 (Sep. 1989).
H. Schumacher et al., "CMOS Subnanosecond True-ECL Output Buffer," IEEE Journal of Solid-State Circuits, vol. 25, No. 1, pp. 150-154 (Feb. 1990).
Wooley et al., "Active Substrate System Integration," Private Communication, Semiconductor Research Corporation, 4 pages (Mar. 15, 1988).
Farmwald Michael
Horowitz Mark
Nguyen Viet Q.
Rambus Inc.
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