Integrated circuit having self-aligned CVD-tungsten/titanium con

Details Integrated circuit having self-aligned CVD-tungsten/titanium con Integrated circuit having self-aligned CVD-tungsten/titanium con

1997-12-19

1999-11-23

Utech, Benjamin

Semiconductor device manufacturing: process

Chemical etching

Liquid phase etching

438745, 438754, 438755, 438756, 438757, 438753, H01L 21336

Patent

active

059900210

ABSTRACT:
This invention is a process for manufacturing a random access memory array. Each memory cell within the array which results from the process incorporates a stacked capacitor, a silicon nitride coated access transistor gate electrode, and a self-aligned high-aspect-ratio digit line contact having a tungsten plug which extends from the substrate to a metal interconnect structure located at a level above the stacked capacitor. The contact opening is lined with titanium metal which is in contact with the substrate, and with titanium nitride that is in contact with the plug. Both the titanium metal and the titanium nitride are deposited via chemical vapor deposition reactions.

REFERENCES:
patent: 5032530 (1991-07-01), Lowrey et al.
patent: 5134085 (1992-07-01), Gilgen et al.
patent: 5846881 (1998-12-01), Sandhu et al.

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