Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
1996-03-14
2001-12-11
Williams, Alexander O. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S758000, C257S765000, C257S764000, C257S759000, C257S751000, C257S741000, C257S774000
Reexamination Certificate
active
06329717
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to insulator layers formed within integrated circuits. More particularly, the present invention relates to silicon oxide insulator spacer layers selectively deposited within patterned metal conductor layers within integrated circuits.
2. Description of the Related Art
Integrated circuits are typically fabricated from semiconductor substrates upon whose surfaces are formed a multiplicity of active semiconductor regions. Within those active semiconductor regions are formed transistors, resistors, diodes and other electrical circuit elements. Those electrical circuit elements are interconnected internally and externally to the semiconductor substrates upon which they are formed through the use of conductor metal layers which are separated by insulator layers.
In accord with the continuing evolutionary trend in semiconductor technology, conductor metal line-widths and spacings within advanced semiconductor integrated circuits have continued to decrease while aspect ratios of those conductor metal lines have continued to increase. As a result of these factors, it is frequently desirable in advanced semiconductor integrated circuits to develop methods and materials through which there may be formed between adjoining patterned conductor metal layers insulator spacer layers which possess excellent gap filling and planarizing properties. Insulator spacer layers which possess excellent gap filling and planarizing properties are most likely to provide void free insulator spacer layers which provide superior substrates for over-lying insulator layers which may provide additional gap- filling and planarizing properties.
It is towards the goal of developing silicon oxide insulator spacer layers which possess excellent gap filling and planarizing properties that the present invention is directed.
Methods by which there may be formed upon semiconductor substrates various types of layers which have specific growth properties, such as gap filling and planarizing properties, are known in the art. For example, Verma in U.S. Pat. No. 4,717,687 describes a method for growing thermal oxides at different rates upon different portions of a semiconductor substrate. The method derives from different growth rates for thermal oxides grown from crystalline silicon semiconductor substrate regions in comparison with thermal oxides grown from metastable amorphous silicon semiconductor substrate regions.
In addition, Yu in U.S. Pat. No. 5,302,555 discloses a method for preferentially depositing a silicon oxide coating on horizontal surfaces of structured semiconductor substrates. The method involves control of several parameters related to the gaseous reactant mixture from which is deposited the silicon oxide coating and several additional parameters related to design of the reactor within which is deposited the silicon oxide coating. Significant parameters which are controlled include the flow ratio of reactant gases, the reactor pressure and the geometry of the susceptor within the reactor.
Still further, Wang et al., in U.S. Pat. Nos. 4,872,947 and 5,354,715, and E. J. Korczyski et al., in “Improved Sub-Micron Inter-Metal Dielectric Gap-Filling TEOS/Ozone APCVD,” Microelectronics Tech., January 1992, pp. 22-27, describe process methods and process hardware for forming planarizing silicon oxide insulating layers through an ozone assisted Chemical Vapor Deposition (CVD) process employing Tetra Ethyl Ortho Silicate (TEOS) as the silicon source material.
Most pertinent to the present invention, however, is the disclosure of Hieber et al. in U.S. Pat. No. 5,399,389. Hieber discloses a method for locally and globally planarizing a structured semiconductor substrate with a silicon oxide layer formed through an ozone activated Chemical Vapor Deposition (CVD) process. The method employs a structured semiconductor substrate fabricated from materials at the lower levels of the structure which have inherently increased growth rates for silicon oxide layers formed through an ozone activated Chemical Vapor Deposition (CVD) process. The method preferably employs a Boro Phospho Silicate Glass (BPSG) or a Phospho Silicate Glass (PSG) lower layer. Optionally, the method also employs a Plasma Enhanced Chemical Vapor Deposited (PECVD) silicon oxide upper layer to retard growth upon metallization layers which otherwise typically form upper layers of the structured semiconductor substrate.
Desirable in the art are methods and materials which expand from the Hiebert disclosure and yield silicon oxide insulator spacer layers which provide a superior substrate for overlying silicon oxide insulator layers, such as over-lying gap filling and planarizing silicon oxide insulating layers, within advanced integrated circuits. Most desirable are silicon oxide insulator spacer layers which may be formed selectively between adjoining patterned metal layers within an advanced integrated circuit and not upon the top surfaces of those adjoining patterned metal layers. Such selectively deposited silicon oxide insulator spacer layers would avoid the need for substantial additional processing, such as etchback processing and sputtering processing, to remove thick portions of silicon oxide insulator spacer layers formed upon surfaces of those adjoining patterned metal layers.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide a silicon oxide insulator spacer layer selectively deposited between adjoining patterned metal layers within an integrated circuit, but not on the surfaces of those adjoining patterned metal layers.
A second object of the present invention is to provide a silicon oxide insulator spacer layer in accord with the first object of the present invention, which silicon oxide insulator spacer layer is readily manufacturable.
A third object of the present invention is to provide a silicon oxide insulator spacer layer in accord with the first object of the present invention and the second object of the present invention, which silicon oxide insulator spacer layer is economical.
In accord with the objects of the present invention, a silicon oxide insulator spacer layer for use within patterned metal layers within integrated circuits is described along with a method by which the silicon oxide insulator spacer layer is formed. To form the silicon oxide insulator spacer layer of the present invention, there is first formed upon a semiconductor substrate a silicon oxide insulator substrate layer, which silicon oxide insulator substrate layer is formed through a Plasma Enhanced Chemical Vapor Deposition (PECVD) process. Upon the silicon oxide insulator substrate layer is formed a patterned multi-metal stack. The patterned multi-metal stack is comprised of a top barrier metal layer formed from titanium nitride and a lower conductor metal layer formed from an aluminum containing alloy. Finally, there is formed selectively upon the portions of the silicon oxide insulator substrate layer exposed through the patterned multi-metal stack and upon the edges of the aluminum containing alloy conductor metal layer exposed through the patterned multi-metal stack a silicon oxide insulator spacer layer. The silicon oxide insulator spacer layer is formed through an ozone assisted Chemical Vapor Deposition (CVD) process for a deposition time not exceeding an incubation time for forming the silicon oxide insulator spacer layer upon the surface of the titanium nitride top barrier metal layer.
The silicon oxide insulator spacer layer of the present invention is formed selectively between adjoining patterned metal layers within an integrated circuit, but not on the surfaces of those adjoining metal layers. It has been found experimentally that the rate of formation of the silicon oxide insulator spacer layer through the ozone assisted Chemical Vapor Deposition (CVD) method of the present invention depends strongly upon the substrate upon which the silicon oxide insulator spacer layer is formed. Within the present invention the silicon oxide
Chen Lung
Jang Syun-Ming
Wu Lin-June
Yu Chen-Hua
Ackerman Stephen B.
Saile George O.
Szecsy Alek P.
Taiwan Semiconductor Manufacturing Company
Williams Alexander O.
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