Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2001-09-13
2002-11-19
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S538000, C257S572000, C257S577000, C330S307000, C330S311000, C330S292000, C330S265000
Reexamination Certificate
active
06483168
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuit implementations of high-speed amplifiers, and more specifically to a preferred implementation of a gain-setting resistor in a high-speed amplifier integrated circuit.
2. Description of the Related Art
FIG. 1
is a schematic diagram of a high-speed cascode amplifier for driving a cathode ray tube (CRT) of a display device (e.g., an HDTV CRT). The amplifier has an input buffer stage, a cascode gain stage, and a cascode Darlington push-pull output stage biased at Class B for driving the cathode of a CRT. The circuit asserts amplified output potential Vout at an output node in response to input potential Vin, when biased by bias potential Vb (when supply voltage Vcc−Vee is applied across its top and bottom rail). The
FIG. 1
amplifier includes cathode current detection circuitry (including PNP transistors X
10
and X
12
and resistors R
12
and R
13
, connected as shown) from which an output signal (I
out
) indicative of the cathode current can be drawn (by circuitry not shown in
FIG. 1
) from node T of FIG.
1
.
The
FIG. 1
amplifier is typically implemented as an integrated circuit (or portion of an integrated circuit), with some or all of its resistors comprising layers of polysilicon over a layer of field oxide (with a substrate of P-type semiconductor material under the field oxide layer). Such an integrated circuit implementation will be assumed in the following description.
In
FIG. 1
, resistors RC
1
and RC
2
are connected in series between nodes X and Y. Node X is coupled to the top rail, which is at potential Vcc. Node Y is coupled to the base of transistor X
7
, to the collector of transistor X
4
, and to one end of resistor R
8
.
Supply voltage (Vcc−Vee) is typically a high voltage (e.g., 145 volts), and input potential Vin typically varies rapidly during operation.
In typical integrated circuit implementations of the
FIG. 1
amplifier, each of resistors RC
1
and RC
2
comprises a polysilicon strip (or multiple polysilicon strips connected in series) over a layer of field oxide, with a substrate of P-type semiconductor material under the field oxide layer.
FIG. 2
is a diagram of one such implementation of portion
2
(including resistors RC
1
and RC
2
) of FIG.
1
. As shown in
FIG. 2
, resistor RC
1
comprises polysilicon strips RS
1
and RS
2
and metal connector M
2
which connects strip RS
1
with strip RS
2
. Resistor RC
2
comprises polysilicon strips RS
3
and RS
4
and metal connector M
4
which connects strip RS
3
with strip RS
4
. Metal contact M
1
(which is node X of
FIG. 1
) is coupled between one end of resistor RC
1
and the top rail of FIG.
1
. Metal connector M
3
connects the other end of resistor RC
1
with one end of resistor RC
2
. Metal contact M
5
(which is node Y of
FIG. 1
) is coupled between the other end of resistor RC
2
and the base of transistor X
7
(shown in FIG.
1
).
A field oxide layer (not shown in
FIG. 2
, to allow substrate
3
to be shown) is deposited on the exposed upper surface of substrate
3
. The four parallel strips RS
1
, RS
2
, RS
3
, and RS
4
of polysilicon are deposited on the oxide layer, and metal connectors M
2
, M
3
, and M
4
(and metal contacts M
1
and M
5
) are deposited on the indicated portions of strips RS
1
-RS
4
and the oxide layer.
A limitation of the above-described implementation of resistor RC
2
(as a polysilicon resistor having the structure described with reference to
FIG. 2
) is that the stray capacitance of such polysilicon resistor (over the field oxide on which it is formed) slows down the output transient response of the
FIG. 1
amplifier. Thus, the absolute value of the amplifier's gain is necessarily reduced in order to achieve faster transient response (by implementing resistor RC
2
with reduced resistance).
U.S. Pat. No. 5,977,610, issued on Nov. 2, 1999 (and assigned to the assignee of the present invention), discloses polysilicon resistor structures other than the structure described with reference to
FIGS. 1 and 2
. U.S. Pat. No. 5,977,610 describes several ways to form a polysilicon resistor over one tub or multiple tubs of N-type semiconductor material in a substrate of P-type semiconductor material.
FIG. 3
is a schematic diagram of a high-speed cascode amplifier which differs from the
FIG. 1
amplifier only in that resistor RC
2
is implemented as a polysilicon resistor of one of the types disclosed in U.S. Pat. No. 5,977,610, in order to reduce its stray capacitance over the field oxide on which it is formed, and thus to improve the amplifier's output transient response without reducing the absolute value of its gain. Portion
12
of the
FIG. 3
circuit (including resistor RC
2
, a diode that underlies RC
2
, and resistor RC
1
) is implemented as shown in FIG.
4
.
As shown in
FIG. 4
, resistor RC
1
is implemented in the same way as in FIG.
2
and the description of its structure will not be repeated with reference to FIG.
4
. In
FIG. 4
, resistor RC
2
comprises polysilicon strips RS
3
and RS
4
and metal connector M
4
connecting strip RS
3
with strip RS
4
. Metal connector M
3
connects one end of resistor RC
2
with one end of resistor RC
1
. Metal contact M
5
(which is node Y of
FIG. 3
) is coupled between the other end of resistor RC
2
and the base of transistor X
7
(shown in FIG.
3
).
Resistor RC
2
of
FIG. 4
(and the amplifier of
FIG. 3
including it) is manufactured on substrate
3
of P-type semiconductor material. At the location on substrate
3
where resistor RC
2
is to be formed, a diode is implemented by forming a layer of N-type semiconductor material
4
on substrate
3
(such as by implanting N-type impurities in a rectangular region of the substrate material and then removing unwanted portions of the N-type semiconductor material). After the initial formation step, layer
4
has uniform (relatively small) thickness, except that it has relatively large thickness at one portion under which metal contact M
6
is to be formed (so that layer
4
extends all the way up to contact M
6
).
After the initial step in forming N-type layer
4
on P-type substrate
3
, layer
4
is enlarged by growing an epitaxial layer of N-type semiconductor material over the initially formed N-type material (except for the thick portion of the N-type material on which contact M
6
is to be formed) and over a portion of P-type substrate
3
surrounding the outer periphery of the initially formed N-type material.
FIG. 4
shows P-type semiconductor substrate material
3
surrounding the outer periphery of completely formed N-type semiconductor layer
4
. Completely formed N-type semiconductor layer
4
comprises a large, single tub (well) of N-type semiconductor material in P-type substrate
3
.
A field oxide layer is deposited on the exposed upper surfaces of substrate
3
and completely formed tub
4
of circuit portion
12
, but not over the portion of tub
4
on which contact M
6
is to be formed. The field oxide layer is not shown in
FIG. 4
to allow depiction of substrate
3
and tub
4
. After deposition of the field oxide layer, parallel polysilicon strips RS
1
, RS
2
, RS
3
, and RS
4
are deposited on the field oxide layer. Finally, a pattern of metal (having high electrical conductivity) is deposited on portions of the polysilicon material, on portions of the field oxide layer between the polysilicon strips, and on the bare portion of tub
4
, to implement metal contacts and connectors M
1
, M
2
, M
3
, M
4
, M
5
, and M
6
. Thus, the completed resistor RC
2
comprises strip RS
3
(connected at one end to connector M
3
and at the other end to connector M
4
) and strip RS
4
(connected at one end to connector M
4
and at the other end to contact M
5
), overlying tub
4
of N-type semiconductor material. Metal contact M
1
of resistor RC
1
is coupled to node X (of
FIG. 3
) so that current can flow from contact M
1
through resistor RC
1
and connector M
3
to one end of polysilicon resistor RC
2
, and then through
Flynn Nathan J.
Girard & Equitz LLP
Mandala Jr. Victor A.
National Semiconductor Corporation
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