Integrated circuit having protection of low voltage devices

Details Integrated circuit having protection of low voltage devices Integrated circuit having protection of low voltage devices

1999-01-20

2000-07-18

Nguyen, Viet Q.

Static information storage and retrieval

Powering

365174, 36518518, 36518527, 257339, 257499, 257500, 257502, H01L 2912

Patent

active

060916575

ABSTRACT:
When flash memory devices are scaled down into the deep-submicron regime, tub erase is being increasingly deployed because it features lower erase current and better reliability performance than the conventional source-side erase scheme. However, tub erase requires higher voltages to be applied to the flash memory device. In a typical design, during tub erase 10 to 12 volts is applied to the tub, source and drain, and -6V is applied to the control gate of the flash memory device. However, in the state-of-the-art CMOS processes (usually used at a power supply voltage 3.3 V and below), it is difficult to build high voltage (HV) devices to support source/drain voltages of more than 6 volts unless the process complexity is significantly increased. Therefore, the required HV devices prevent tub erase from being widely used, especially for embedded applications. In the present invention, a separate protection tub is added to the on-pitch devices close to the memory array, and all these on-pitch devices share the same protection tub. While the main cell array tub is biased at 10 to 12 volts during tub erase, an intermediate voltage, 6 volts for example, can be used to bias the protection tub, which prevents the junction breakdown of those peripheral devices. At times other than tub erase, the protection tub is biased at 0 volts. Therefore, the high voltages of 10 to 12 volts are isolated by 6 volt triple-tub CMOS devices, and it becomes feasible to embed an advanced tub-erase flash memory in a CMOS logic process.

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"High Voltage CMOS Logic Circuit Using Low Voltage Transistors," Cochran-McLellan, Case 18-4, Serial #08/985709, filed on Dec. 5, 1997, 12 pages.

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