Integrated circuit having power trunk line and method for layout

Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular power supply distribution means

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257202, 257211, 437180, 326101, H01L 2702, H01L 2710

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active

053919009

ABSTRACT:
The present invention relates to an integrated circuit comprising a semiconductor chip having thereon a logical function portion for realizing logical function and at least one power supply point for supplying electric power to the logical function portion, and at least one first, second and third power trunk line are arranged on the chip for supplying electric power from the power supply point to the logical function portion. The second power trunk line is disposed in an area in which the logical function portion of the chip is disposed. The first power trunk line is disposed between the power supply point and the second power trunk line to connect the second power trunk line with the power supply point. The third trunk line is connected at at least one end to the second trunk line and is disposed in the logical function portion for supplying electric power to the logical function portion.

REFERENCES:
patent: 4625227 (1986-11-01), Hara et al.
patent: 4811073 (1989-03-01), Kitamura et al.
patent: 4947229 (1990-08-01), Tanaka et al.
patent: 5008728 (1991-04-01), Yamamura et al.
"A 400K-Transistor CMOS Sea-of-Gates Array with Continuous Track Allocation", IEEE Journal of Solid-State Circuits, vol. 24, No. 5, Oct. 1989, pp. 1280-1286 Masatomi Okabe et al.

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