Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Charge transfer device
Reexamination Certificate
2002-01-11
2003-12-30
Cuneo, Kamand (Department: 2829)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Charge transfer device
C257S053000, C257S054000, C257S055000, C257S056000, C257S183000, C257S183100, C257S184000, C257S185000, C257S186000, C257S187000, C257S188000, C257S189000, C257S190000, C257S226000, C257S227000, C257S228000, C257S229000, C257S230000, C257S231000, C257S232000, C257S233000, C257S234000, C257S277000, C257S292000, C257S430000, C438S059000, C438S081000, C438S096000
Reexamination Certificate
active
06670657
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority from prior French Patent Application No. 01-00420, filed Jan. 12, 2001, the entire disclosure of which is herein incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuits, and more specifically to integrated circuits that include photodiode-type semiconductor devices.
2. Description of Related Art
To produce a good photodiode is tricky. This is because it has to be sensitive to light and only the space charge region of the junction is capable of collecting the carriers generated by the light excitation, because of the electric field existing in this region. Now, a photodiode is more sensitive the larger the space charge region. This means that the doping gradient at the junction is low. However, if the doping gradient is low, the capacitance of the junction is also low. Now, the role of a photodiode is to store, in this junction capacitor, the carriers generated in the space charge region.
The solution normally used consists in increasing the doping gradient of the junction and the voltage applied to this junction. It is thus possible to obtain a wide space charge region combined with a high junction capacitance. Typically, a voltage of greater than 5 volts must be applied if the doping levels are high. However, current submicron integrated circuits do not allow high voltages to be used since. In these technologies, the maximum supply voltage is less than 3.3 volts.
SUMMARY OF THE INVENTION
In view of these drawbacks, it is an object of the present invention to overcome the above-mentioned drawbacks and to decorrelate the doping gradient of the junction from the capacitance of the junction.
Another object of the present invention is to reduce the doping gradient at the junction so as to obtain a large extension of the space charge region even for low applied voltages.
Yet another object of the present invention is to increase the capacitance associated with the junction, while neither increasing the footprint nor reducing the sensitivity of the photodiode for a given surface area.
A further object of the present invention is to produce a single-crystal substrate that allows the subsequent formation of an epitaxial silicon layer free of crystal defects, in which layer a junction can be formed.
One embodiment of the present invention provides an integrated circuit that includes a substrate incorporating a semiconductor photodiode device having a p-n junction. The photodiode device includes at least one capacitive trench buried in the substrate and connected in parallel with the junction. In a preferred embodiment, the substrate is formed from silicon, and the capacitive trench includes an internal doped silicon region partially enveloped by an insulating wall that laterally separates the internal region from the substrate.
Another embodiment of the present invention provides a method for fabricating an integrated circuit including a substrate that incorporates a semiconductor photodiode device having a p-n junction. According to the method, there is produced an initial single-crystal substrate having locally a capacitive trench emerging at the surface of the initial substrate and forming a discontinuity in the crystal lattice. The initial substrate is recessed at the trench, and the crystal lattice is amorphized around the periphery of the recess. A layer of amorphous material having the same chemical composition as the initial substrate is deposited, and a thermal annealing is performed in order to recrystallize the amorphous material so as to be continuous with the single-crystal lattice of the initial substrate. An upper substrate layer is grown epitaxially. In one preferred method, the junction is formed by n
+
-type surface codiffusion of arsenic and phosphorus.
Other objects, features, and advantages of the present invention will become apparent from the following detailed description. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the present invention, are given by way of illustration only and various modifications may naturally be performed without deviating from the present invention.
REFERENCES:
patent: 5307169 (1994-04-01), Nagasaki et al.
patent: 6318906 (2001-11-01), Ishizaka
patent: WO99/48152 (1999-09-01), None
“One-Device CMOS Dram Cell with Buried Poly Trench and Drain Reach Through,” IBM Technical Disclosure Bulletin, pp. 451-452, vol. 30, No. 11, Apr. 1988.
“Vertical Conducting Connection to a Poly-Si Trench In Si,” IBM Technical Disclosure Bulletin, pp. 310-312, vol. 31, No. 12, May 1989.
Preliminary Search Report dated Oct. 19, 2001 for French Patent Application No. 0100420.
Gris Yvon
Menut Olivier
Bongini Stephen
Cuneo Kamand
Fleit Kain Gibbons Gutman Bongini & Bianco P.L.
Jorgenson Lisa K.
Kilday Lisa
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