Integrated circuit having permanent adjustment circuitry which r

Electrical resistors – Incased – embedded – or housed – Element in insulation with outer metallic sheath

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357 13, 338 92, H01L 2704, H01C 1018

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047758848

ABSTRACT:
An integrated circuit resistor adjustment network with resistors (R1, R2, R3, R4) which may be paralleled by trimming resistors (R5, R7, R6, R8, respectively) upon electrical "zapping" of Zener diodes (Z1, Z2, Z3, Z4, respectively) connected in series with the trimming resistors. The Zener diodes (Z1, Z4 or Z2, Z3) are connected in inverse series via inverse paralleled diodes (D1, D2 or D3, D4 respectively) which are non-conductive during normal operation, but conduct during higher voltage zapping operation to permit the currents for zapping the Zener diodes to bypass the resistors. By having the trimming resistors in two branches (R1, R5, R4, R6 and R2, R7, R3, R8 respectively) so arranged that in one branch a resistor of value 4R may be paralleled with a 1R resistor and an 8R resistor may be paralleled with a 2R resistor, and in the other branch, a 4R resistor may be paralleled with an 2R resistor and an 8R resistor may be paralleled with a 1R resistor, offsets can be trimmed in either direction in approximately equally spaced steps.

REFERENCES:
patent: 4412241 (1983-10-01), Nelson
patent: 4451839 (1984-05-01), Nelson
Lin, Integrated Electronics, (Holden-Day, San Francisco, 1967) pp. 227-229.

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