Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2003-03-24
2004-11-02
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S499000, C257S506000, C257S516000, C257S528000, C438S421000, C438S624000, C438S631000, C438S633000, C438S689000, C438S692000
Reexamination Certificate
active
06812544
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to integrated circuits and more particularly to components that comprise an integrated circuit.
BACKGROUND OF THE INVENTION
The general structure of an integrated circuit is known to include one or more dielectric layers on a substrate. As is further known, each of the dielectric layers supports a metal layer, which is etched or deposited to form integrated circuit components such as resistors, capacitors, inductors, transistors, conductive traces, et cetera. The number of dielectric layers, and hence the number of metal layers, along with acceptable physical dimensions of the dielectric layers and metal layers are dictated by the particular type of integrated circuit technology and the corresponding integrated circuit fabrication rules. For example, a CMOS integrated circuit may include multiple dielectric layers and multiple corresponding metal layers. Depending on the particular foundry rules, the size of each dielectric layer and corresponding metal layers have prescribed minimum and maximum dimensions. In addition, such foundry rules prescribe maximum dimensions for metal tracks formed on the metal layers. For instance, the maximum metal track may be 30-40 microns for a given CMOS process. As is known, IC foundries provide the maximum metal track dimensions to prevent over-stressing the integrated circuit and/or to ensure reliability of fabrication.
As is also known, integrated circuit foundries provide minimum spacing between metal tracks. For example, the minimum spacing may be 1.0 microns to 3.0 microns and may further be dependent on the particular metal layer the track is on and/or the width of adjacent tracks.
Such foundry rules limit the ability to design certain on-chip components. For instance, on-chip inductors designed using CMOS technologies are limited to a quality factor (i.e., Q factor which=2(pi)fL/R, where R=the effective series resistance, L=the inductance and f is the operating frequency) of about 5 to 8 at frequencies of 2.5 gigahertz. Such a low quality factor is primarily due to a significant effective series resistance at 2.5 gigahertz. As is further known, the effective series resistance is dependent on the operating frequency of the component and is further dependent on the size of the metal track. As such, by limiting the size of metal tracks, the quality factor of inductors is limited to low values.
Capacitance values of on-chip metal insulated metal capacitors are also limited due to the foundry rules. As is known, the capacitance of a capacitor is based on the area of its plates, the distance between the plates, and the dielectric properties of the dielectric material separating the plates. Since the foundry rules limit the size of the plates, the capacitor values are limited, which, in turn, limit the uses of on-chip capacitors.
Therefore, a need exists for a technique to increase the effective size of metal tracks while maintaining compliance with foundry metal track rules and to allow for greater range of design of on-chip integrated circuit components.
SUMMARY OF THE INVENTION
These needs and others are substantially met by the integrated circuit described herein. Such an integrated circuit includes electrical components that include one or more electrical elements on one or more dielectric layers. The electrical element, which may be a winding(s) of an inductor, power source trace, gate of a transistor, source of a transistor, drain of a transistor, plate of a capacitor, resistor, electromagnetic shield, ground plane et cetera, has a geometric shape that exceeds prescribed integrated circuit manufacturing limits. For example, if the integrated circuit manufacturing limits prescribe metal tracks not to exceed 35 microns in width or length, the electrical element of the present invention has a dimension in width and length that exceeds 35 microns. To achieve compliance with foundry rules, the electrical element is fabricated to include a non-conducting region that negligibly effects the electrical characteristics. For instance, the electrical element may be fabricated to include a hole, a series of holes, a slot and/or a series of slots spaced within the electrical element at dimensions that are less than the integrated circuit manufacturing limits.
REFERENCES:
patent: 5686356 (1997-11-01), Jain et al.
Contopanagos Harry
Komninakis Christos
Broadcom Corp.
Huynh Andy
Markison Timothy W.
Nelms David
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