Integrated circuit having output timing control circuit and meth

Details Integrated circuit having output timing control circuit and meth Integrated circuit having output timing control circuit and meth

1998-03-27

2000-01-04

Nguyen, Tan T.

Static information storage and retrieval

Addressing

Sync/clocking

365194, 395556, G11C 800

Patent

active

060117494

ABSTRACT:
An integrated circuit memory having a plurality of memory cells, output timing control means including frequency measurement means providing a frequency measurement count corresponding to a first frequency of the external clock signal and delay control means generating a delayed clock signal at the first frequency, wherein the delayed clock signal is delayed in time from the external clock signal in proportion to the first frequency, and data output control means outputting data from the plurality of memory cells responsive to the delayed clock signal. A method for adjusting output timing in a memory device including the steps of receiving an external clock signal, measuring a frequency of the external clock signal, generating a frequency count, determining an output delay proportional to the frequency, and generating an output clock at the external frequency and delayed from the external clock signal in proportion to the frequency.

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Motorola Inc. 1998, Semiconductor Technical Data, "Advance Information 128K.times.36 and 256K.times.18 Bit Pipelined ZBT.TM. RAM Synchronous Fast Static RAM", pp. 1-20.

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