Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular signal path connections
Reexamination Certificate
2003-09-15
2004-10-12
Nguyen, Van Thu (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular signal path connections
C257S208000, C257S210000, C257S211000
Reexamination Certificate
active
06803612
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present application relates to an integrated circuit having electrical connecting elements that each have a first conductivity state or a different, second conductivity state that can be brought about by impressing energy.
Electrical connecting elements that have a first state or a second state are also referred to as fuses. In such a case, a distinction is made between, for example, laser fuses and electrical fuses. Laser fuses are programmed by the light emitted by a laser. In contrast thereto, electrical fuses are programmed by an electric current that flows through the fuses. In the case of electrical fuses, a distinction is made between fuses and antifuses, depending on whether the electrical connecting element is conducting or non-conducting in the non-programmed state. Fuses are usually only one-time programmable.
Fuses are used, for example, in integrated circuits in order, after a functional test, to replace a defective function block of the integrated circuit by a redundant function block. Laser fuses are usually configured such that they firstly form a conducting connection. A laser programs a laser fuse by a laser beam destroying the conducting connection. From a general standpoint, it is possible to form fuses from any desired conducting material. By way of example, the fuses can be produced from a metal. The fuses are usually disposed in a delimited region of the substrate surface. This region is referred to, for example, as laser fuse bay or fuse bank. The fuses disposed in the fuse bank are usually at a predetermined distance from one another. If the fuses are disposed at an excessively small distance from adjacent fuses, then it is possible, during the programming of a fuse, for an adjacent fuse to be damaged by the absorption of reflected or direct laser light. Equally, it is possible for a fuse that has already been programmed and, thus, severed to be short-circuited by material that is released during the programming of a fuse adjacent thereto.
The need to comply with a relatively large distance between adjacent fuses will lead to problems in the future because the area that can be utilized for an integrated circuit is continually being reduced so that the laser fuse bay must, likewise, be reduced in size.
It is known from the prior art that the distance between two adjacent fuses can be reduced if so-called staggered fuses are formed. In such a case, the material that can be severed by the laser is fabricated in a first metal layer and the lead to the laser-programmable material is fabricated in a second metallization plane that is disposed above that and, for example, is disposed nearer to the substrate surface than the first metal layer. The lead is led, for example, by a contact hole from the first wiring plane (first metal layer) to the second wiring plane (second metal layer). In the case of staggered fuses, it is problematic that, during the programming of a fuse, the laser beam can damage the leads for adjacent fuses that are disposed in the deeper wiring planes.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated circuit having electrical connecting elements that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and that is space-saving and, in the case of programming by a laser, avoids damage to adjacent interconnects or fuses.
With the foregoing and other objects in view, there is provided, in accordance with the invention, an integrated circuit has electrical connecting elements that each have a first conductivity state or a different, second conductivity state that can be brought about by impressing energy, including:
a substrate having a substrate surface, which has a first extension direction and a second extension direction, running perpendicularly thereto;
a first electrical connecting element and a second electrical connecting element, which, as seen in the second direction, are disposed next to one another above the substrate surface in a first wiring plane;
a third electrical connecting element and a fourth electrical connecting element, which, as substantially seen in the second direction, are disposed next to one another on the substrate surface;
one end of the third electrical connecting element and one end of the fourth electrical connecting element being spaced apart along the first direction from one end of the first electrical connecting element and one end of the second electrical connecting element;
the first electrical connecting element, as seen in the second direction, being at a first distance from the second electrical connecting element;
a first interconnect, which is disposed above the substrate surface and is connected to the first electrical connecting element;
a second interconnect, which is disposed above the substrate surface and is connected to the second electrical connecting element;
the first interconnect and the second interconnect being disposed between the third electrical connecting element and the fourth electrical connecting element and therebetween having a second distance, which is smaller than the first distance;
and the first interconnect being disposed in the first wiring plane and the second interconnect being disposed at least partly in a second wiring plane, which is located nearer to the substrate surface than the first wiring plane.
One advantage of the configuration according to the invention is that the electrical connecting elements are spaced apart on the substrate surface by a first distance that is, advantageously, chosen to avoid damage to fuses during the programming of an adjacent fuse. Furthermore, interconnects are disposed on the substrate surface such that they are at a smaller distance than the electrical connecting elements connected to them. This has the advantage that interconnects can be disposed very compactly on the substrate surface. In addition, the interconnects are disposed on the substrate surface such that they run between two adjacent electrical connecting elements.
The distance between the electrical connecting elements is, advantageously, likewise chosen such that an adjacent, already programmed fuse is not short-circuited by material that is removed during the programming of the fuse. The configuration according to the invention makes it possible to reduce the substrate surface required for a fuse bank, with the number of electrical connecting elements in the fuse bank kept constant.
In accordance with a further feature of the invention, the first interconnect and the second interconnect are disposed next to one another as seen in the direction of a normal to the substrate, the normal being disposed perpendicular to the substrate surface. As a result, two or more interconnects are disposed one above the other on the substrate surface between two electrical connecting elements. Such a configuration has the advantage that the interconnects that are connected to electrical connecting elements can be formed very compactly and closely adjacent to one another.
In accordance with another feature of the invention, the first and second interconnects are disposed in an at least partly overlapping manner as seen in a direction of a normal to the substrate, the normal being disposed perpendicular to the substrate surface.
In the integrated circuit, a first wiring plane and a second wiring plane are disposed on the substrate surface, the first wiring plane being at a different distance from the substrate surface than the second wiring plane. Towards the substrate surface, the first wiring plane is at a greater distance than the second wiring plane. The second wiring plane is located nearer to the substrate surface than the first wiring plane. The first wiring plane is expediently the topmost wiring plane of the integrated circuit. This enables a space-saving configuration of interconnects because interconnects can be spaced apart from one another in the direction of the normal to the substrate, with the result that the interconnect
Lehr Matthias Uwe
Möckel Jens
Többen Dirk
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
Menz Doug
Nguyen Van Thu
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