Integrated circuit having efficiently packed decoupling...

Details Integrated circuit having efficiently packed decoupling... Integrated circuit having efficiently packed decoupling...

2010-03-12

2010-12-28

Lee, Calvin (Department: 2892)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular signal path connections

C438S129000

Reexamination Certificate

active

07859024

ABSTRACT:
An integrated circuit includes a substrate having a semiconducting surface (605) and a plurality of standard cells arranged in a plurality of rows including at least a first row (610) and a second row (615) immediately above the first row. The first row (610) include at least a first decap filler cell (602) including a first active area (612) and a field dielectric outside the first active area (612) having a portion with a full field dielectric thickness portion621and a portion with a thinned field dielectric (622), and at least a first MOS transistor (618) having a gate electrode (619) on a thick gate dielectric (613) on the first active area (612) connected as a decoupling capacitor. The second row (615) includes a second decap filler cell (601) including an active area (632) and a field dielectric portion (621) and thinned field dielectric portion (622), at least a second MOS transistor (638) having a gate electrode (639) on the thick gate dielectric (613) on the second active area (632) connected as a decoupling capacitor. The thinned field dielectric (622) extends from the first decap filler cell (602) to the second decap filler cell (601) across a border (608) between the first and second decap filler cell. A method of forming an integrated circuit including high efficiency decap filler cells includes the step of gap filling a thick gate dielectric mask.

REFERENCES:
patent: 7137092 (2006-11-01), Maeda
patent: 7709301 (2010-05-01), Bosshart
patent: 7763534 (2010-07-01), Smayling et al.

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