Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Patent
1996-07-23
1998-12-29
Everhart, Caridad
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
257773, 257920, 257923, 257748, 257763, 257765, H01L 2352
Patent
active
058545158
ABSTRACT:
A interconnect structure is provided having a conductor with enhanced thickness. The conductor includes an upper portion and a lower portion, wherein the lower portion geometry is sufficient to increase the current-carrying capacity beyond that provided by the upper portion. The lower portion is formed by filling a trench within an upper dielectric region, and the upper portion is formed by selectively removing a conductive material from the upper dielectric surface except for regions directly above the lower portion. The upper and lower portions thereby form a conductor of enhanced cross-section which can be produced by modifying a via-etch mask, rather than having to reconfigure and/or move interconnect features formed by a metal mask.
REFERENCES:
patent: 4905068 (1990-02-01), Satoh et al.
patent: 5385867 (1995-01-01), Ueda et al.
patent: 5571751 (1996-11-01), Chung
patent: 5602050 (1997-02-01), Sudo
K. Ueno, et al. "Quarter Micron Planarized Interconnection Tech. With Self-Algned Plug" IEDM (Dec. 1992) pp. 305-308.
Bandyopadhyay Basab
Brennan William S.
Dawson Robert
Fulford Jr. H. Jim
Hause Fred N.
Advanced Micro Devices , Inc.
Daffer Kevin L.
Everhart Caridad
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