Static information storage and retrieval – Format or disposition of elements
Reexamination Certificate
2000-02-15
2002-05-28
Nelms, David (Department: 2818)
Static information storage and retrieval
Format or disposition of elements
C365S161000, C365S230060
Reexamination Certificate
active
06396727
ABSTRACT:
TECHNICAL FIELD
The invention relates generally to an integrated circuit having conductive paths of different heights formed in the same layer structure, and more particularly to a memory circuit having one or more digit lines formed from a conductive layer structure having a first thickness and one or more signal lines formed from the conductive layer structure and having a second, greater thickness.
BACKGROUND OF THE INVENTION
To accommodate continuing consumer demand for integrated circuits that perform the same or additional functions and yet have a reduced size as compared with available circuits, circuit designers continually search for ways to reduce the size of the memory arrays within these circuits without sacrificing array performance. One technique for reducing the size of a memory array is to decrease the spacing between adjacent digit lines.
A problem with decreasing this spacing is that it increases the line-to-line coupling capacitance between adjacent digit lines. As the coupling capacitance increases, the memory read and write times are often increased due to the longer time required to charge and discharge the increased line-to-line coupling capacitance. Furthermore, the increased coupling capacitance may cause increased cross talk between adjacent digit lines, and thus may cause reading and writing errors.
Digit-line coupling capacitance is proportional to the side areas of adjacent lines, and is inversely proportional to the distances between them. One technique for reducing digit-line cross coupling is to increase the distance between adjacent digit lines. But this would increase the size of the array, and thus of the circuit containing the array. Reducing the digit-line widths to effectively increase the distances between adjacent digit-lines is often impractical due to process and functional limitations.
Another technique for reducing cross coupling in digit lines is to reduce the height, i.e., thickness, of the lines. But this may cause unwanted effects in other signal lines formed from the same metallization level. For example, the power and ground lines are often formed in the same metallization level as the digit lines. The power and ground lines must be thick enough to carry the required current. But reducing the thickness of this metallization level to reduce the thicknesses of the digit lines would also reduce the thicknesses of the power and ground lines, thus possibly decreasing their current-carrying capacities below acceptable levels.
SUMMARY OF THE INVENTION
In accordance with one aspect of the invention, an integrated circuit includes a substrate having a surface. A first conductive path having a first height is disposed on the substrate at a first level. A second conductive path is also disposed on the substrate at the first level and has a second height that is significantly different than the first height.
Where the integrated circuit is a memory circuit, the digit lines formed from a layer can have a smaller height than other signal lines that are formed from the same layer. Thus, the capacitive coupling between the digit lines is reduced without degrading the current carrying capability of the other signal lines. Furthermore, the reduced coupling capacitance often reduces or eliminates data read/write errors.
REFERENCES:
patent: 4824521 (1989-04-01), Kulkarni et al.
patent: 4958222 (1990-09-01), Takakura et al.
patent: 5055423 (1991-10-01), Smith et al.
patent: 5138403 (1992-08-01), Spitzer
patent: 5331196 (1994-07-01), Lowrey et al.
patent: 5341026 (1994-08-01), Harada et al.
patent: 5363325 (1994-11-01), Sunouchi et al.
patent: 5375095 (1994-12-01), Yamada et al.
patent: 5396100 (1995-03-01), Yamasaki et al.
patent: 5516726 (1996-05-01), Kim et al.
patent: 5543358 (1996-08-01), Jimenez
patent: 5580809 (1996-12-01), Mori et al.
patent: 5658819 (1997-08-01), Humphrey et al.
patent: 5693568 (1997-12-01), Liu et al.
patent: 5730835 (1998-03-01), Roberts et al.
patent: 5818089 (1998-10-01), Kokubo et al.
patent: 5874779 (1999-02-01), Matsuno
patent: 5883007 (1999-03-01), Abraham et al.
patent: 6100590 (2000-08-01), Yegnashankaran et al.
patent: 6178113 (2001-01-01), Gonzalez et al.
patent: 6189582 (2001-02-01), Reinberg et al.
Schoenfeld Aaron
Somasekharan Rajesh
Dorsey & Whitney LLP
Le Thong
Nelms David
LandOfFree
Integrated circuit having conductive paths of different... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated circuit having conductive paths of different..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit having conductive paths of different... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2911706