Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-03-14
2003-12-23
Tran, M. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185240
Reexamination Certificate
active
06667906
ABSTRACT:
BACKGROUND OF THE INVENTION
The most common variety of non-volatile memories, such as EPROM, flash memory, and some EEPROMs, today employs channel hot electron (CHE) for programming and negative gated Fowler-Nordheim (FN) tunneling for erase.
FIG. 1
shows a conventional n-channel stack gate flash memory cell
100
. Memory cell
100
includes N+ source
102
and drain
103
regions spaced apart in a P-type silicon substrate
101
to form a channel region
104
therebetween. A floating gate
105
of polycrystalline silicon material is laid on top of a tunneling dielectric
106
, which extends over the channel region
104
and overlaps the source
102
and drain
103
regions. Stacked on top of, but insulated from, floating gate
105
is a gate
107
of polycrystalline material. Junction
102
is made deeper than normal in order to minimize the adverse reliability effects of tunnel oxide hot hole trapping during erase operation.
Cell
100
is programmed, i.e., its threshold voltage is raised higher, by applying 10V to gate
107
, 5V to drain
103
, and grounding source
102
. The memory cell is thus strongly turned on, and the cell's threshold voltage is raised due to injection of hot electrons from the channel region near the drain
103
to floating gate
106
, as indicated by the arrow labeled as “P”. Cell
100
is erased, i.e., its threshold voltage is lowered, by applying −10V to gate
107
, 5V to source
102
, and floating drain
103
. The cell's threshold voltage is thus lowered due to tunneling of electrons from the floating gate
105
to source
102
, as indicated by the arrow labeled as “E”.
Conventional memory arrays include a matrix of memory cells arranged along rows and columns. The gates of the cells along each row are connected together forming a wordline. In one array architecture, the cells along each column are grouped in a number of segments, and the drains of the cells in each segment are coupled to a corresponding segment line. The segment lines along each column are coupled to a corresponding data line through one or more segment select transistors. The segmentation of the cells in each column helps reduce the bitline capacitance to that of the metal bitline plus the small capacitance of a selected segment line. Performance of the memory is thus improved.
During programming or read operations, one or more bitlines are selected through a column select circuit for transferring data to or from the selected memory cells. The column select circuit typically has a multiplexer configuration in that a group of serially-connected NMOS pass transistors controlled by column decoding signals selectively couple one or more bitlines to either sense amplifiers (read operation) or data-in buffers (programming operation). Depending on the total number of bitlines in the array and the number of bitlines to be selected, two or more levels of column selection need to be implemented in the column select circuit. The number of levels of column selection corresponds to the number of serially-connected pass transistors that couple the selected bitlines to the sense amplifier or data-in buffer. For example, if two levels of column selection are implemented, a selected bitline will be coupled to the sense amplifier or data-in buffer through two serially-connected column select transistors.
The sizes of the column select transistors and the segment select transistors need to be made large enough so that the required cell programming voltage and current can be provided to the selected cell. Because of the programming biasing conditions, the serially connected segment select transistor and column select transistors result in a rather resistive path, which can be compensated for by increasing the transistor sizes. This can be more clearly understood with the help of FIG.
2
.
FIG. 2
shows a portion
201
of an array along with a portion
202
of a column select circuit. The array portion
201
includes a memory cell
100
with its gate coupled to wordline WL and its drain coupled to a segment line S
0
. The source of cell
100
is shown as being connected to ground for simplicity, although, the source is typically connected to a source line which may be decoded to provide ground only to selected memory cells. A segment select transistor MS is coupled between segment line S
0
and bitline BL, with its gate coupled to segment select signal SS. Bit line BL is coupled to the data-in block
204
through two serially connected column select transistors MYa and MYb. Column select transistors MYa and MYb are controlled by column decode signals Ya and Yb, respectively. As indicated in
FIG. 2
, the deeper source junction
102
of the
FIG. 1
cell is connected to ground, while the shallower drain junction
103
is connected to segment line S
0
.
As can be seen, cell
100
, and transistors MS, MYa, and MYb are serially-connected to data-in block
204
. To program cell
100
, 10V is supplied to wordline WL, while 5V needs to be supplied to its drain, i.e., to segment line S
0
. To supply 5V to segment line S
0
, data-in block
204
outputs 5V on line
206
, and column select signals Ya and Yb as well as segment select signal SS are raised to 10V. Thus, the 5V on line
206
is transferred through transistors MYa, MYb, and MS to segment line S
0
. The drive capability of each transistor MYa, MYb, MS is, to a first order approximation, equal to its Vgs−Vt, wherein Vgs represents the transistor gate to source voltage, and Vt represents the transistor threshold voltage. For each of transistors MYa, MYb, MS, Vgs=Vg−Vs=10V−5V=5V, and the Vt is approximately 2V because of the back bias effect. Thus, for each transistor MYa, MYb, MS, Vgs−Vt=5V−2V=3V. Because of the small Vgs−Vt of 3V, the sizes of these transistors need to be made large so that sufficient current can be supplied to the cell during programming.
In higher density memories, where the number of levels in the column select circuit increases, the sizes of the column select transistors increase proportionally. This increases the die size. More importantly, as higher performance is required of memory devices, the need for further segmentation of the bitlines increases, resulting in a larger number of segment select transistors in the array. The adverse impact of a larger size segment select transistor and a larger number of segment select transistors on the overall die size can be rather substantial.
FIG. 3
illustrates another draw back of conventional memory arrays, namely, the non-uniform programming characteristic of memory cells in the array due to the source resistance. A portion
300
of a memory array is shown as including 16 memory cells
100
-
0
to
100
-
15
along a row. The drain of each cell is coupled to a corresponding segment line S
0
to S
15
, and the gates of the cells are connected to a wordline WL. The sources of the cells are connected together and to metal source lines SLn and SLn+1 through a diffusion strip
310
. Resistors R
0
to R
16
depict the resistance associated with the diffusion strip
310
. The cell configuration of
FIG. 3
is repeated as many times as required to form the entire array.
For the above-indicated cell biasing during programming, the cell programming performance is dependent primarily upon the gate to source voltage Vgs of the cell. For example, with the wordline WL at 10V, and the source fully grounded, the cell Vgs equals a full 10V. However, because of the presence of the resistive diffusion strip
310
, depending on the location of the cells along the diffusion strip
310
, the effective Vgs of the cells vary. For example, of the 16 cells, the cells closest to the center of the diffusion strip will have the maximum source resistance, and thus poorer programming characteristics, while the cells closest to the ends of the diffusion strip
310
have minimum source resistance, and thus the best programming characteristics. This leads to the undesirable non-uniform programming characteristics of the c
Park Eungjoon
Pourkeramati Ali
Azalea Microelectronics Corporation
Townsend and Townsend / and Crew LLP
Tran M.
LandOfFree
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