Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to conductive state
Reexamination Certificate
2002-04-30
2004-06-29
Rocchegiani, Renzo (Department: 2825)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Using structure alterable to conductive state
C438S600000, C438S601000, C438S630000, C257S530000, C257S050000, C257S209000
Reexamination Certificate
active
06756254
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention is directed to a method for fabricating integrated circuit having an antifuse and to an integrated circuit with the antifuse.
U.S. Pat. No. 5,780,323, whose disclosure is incorporated herein by reference thereto, discloses a method for fabricating an integrated circuit in which an antifuse structure is formed. For this purpose, a dielectric stack is provided on a first metallization region. As its uppermost layer, the dielectric stack contains an amorphous silicon layer, often referred to as an a-silicon layer. After depositing of the dielectric interlayer, a contact hole is etched and a metal layer is deposited above the resulting structure, forming a boundary surface with the a-silicon layer of the dielectric stack. After a conditioning process, the a-silicon layer of the dielectric stack is converted into a metal silicide layer.
U.S. Pat. No. 5,565,702, whose disclosure is incorporated herein by reference thereto, discloses an antifuse structure and a corresponding fabrication method. In this known method, first, a dielectric interlayer is deposited above a first metallization region, and then the contact holes are provided therein. The antifuse structures are formed in the contact holes.
A similar method is disclosed in Japanese 5-121555 A. U.S. Pat. No. 4,128,670, whose disclosure is incorporated herein by reference thereto, and an article by D. Widmann et al,
Technologie hochintegrierter Schaltung
(
Large
-
scale integrated circuit technology
), 2nd Edition, Springer, 1996, pp. 82-87, disclose the fabrication of silicide layers by depositing metal layers and silicon layers over the entire surface.
Although it can, in principle, be applied to any desired integrated circuits, the present invention and the problem on which it is based are explained in connection with integrated circuits produced using silicon technology.
FIGS. 2
a
-
2
d
diagrammatically depict various process steps involved in a known method for fabricating an integrated circuit using silicon technology.
In
FIG. 2
a
, an insulation layer
2
comprising silicon dioxide is provided on an integrated circuit (not shown) and two metallization regions
10
a
and
10
b
of tungsten have been formed in this insulation layer. The introduction of the metallization regions
10
a
and
10
b
can be achieved, for example, by following a trench etching technique, depositing tungsten over the entire surface above the silicon dioxide layer
2
and then removing the tungsten by chemical and mechanical polishing in such a manner that the separate metallization regions
10
a
and
10
b
are formed.
The intention of the method shown is to allow, in addition to the standard tungsten contacts on the first metallization region
10
a
, a second type of contact also to be created, in which a functional layer
15
rests on top of the second metallization region
10
b
, with which contact is made from above by a contact. In the present case, the functional layer serves as a fusible link or antifuse and consists of SiN/WSi
X
. However, it could also be a metallic barrier layer or the like.
As shown in
FIG. 2
b
, in a subsequent process step, the functional layer
15
of SiN/WSi
X
is deposited above the resulting structure, so that it covers the first and second metallization regions
10
a
and
10
b
. In a subsequent process step, a photomask
20
is formed in such a manner that it covers the functional layer
15
over the second metallization region
10
b
but leaves the functional layer
15
above the first metallization region
10
a
clear.
Then, as shown in
FIG. 2
c
, an etching process and a resist-stripping operation take place, for example in an NF
3
-containing plasma, in order to remove the exposed portions of the functional layer
15
above the first metallization region
10
a
. During this etching operation and during the stripping of the resist, an oxide film
100
comprising WO
X
is formed above the tungsten of the first metallization region
10
a
. A disadvantage is that it is impossible to avoid the formation of the WO
X
layer of this type and, consequently, the contact resistance between the contact
11
a
, which is to be formed later, and the first metallization region
10
a
is undesirably increased.
As shown in
FIG. 2
d
, following the preceding process step, an insulation layer
25
of, for example, silicon dioxide, is deposited over the entire surface of the resulting structure. Then, contact holes
12
a
and
12
b
are formed above the first and second metallization regions
10
a
and
10
b
, respectively, and these holes are filled with contacts
11
a
and
11
b
consisting of tungsten. This filling with the contacts can be effected in a similar manner to the formation of the first and second metallization regions
10
a
and
10
b
by depositing tungsten over the entire surface of the structure, including the contact holes
12
a
and
12
b
, and then partially removing this tungsten again by chemical, mechanical polishing.
A fusible link or antifuse, as is also known from U.S. Pat. No. 5,780,323, is illustrated in FIG.
3
and includes a function layer
30
of amorphous silicon which is deposited above the level of the contact hole
12
comprising the contact
11
and is patterned. After the step of patterning, an interconnect
40
is provided above the resulting structure and this interconnect can be used to blow the fusible link The fact that the layer
30
of amorphous silicon has a considerable thickness and, therefore, requires high voltages and currents in order to be blown, has proven to be a drawback of this type of structure.
An important property of a continuous, i.e., programmed dielectric antifuse structure, consists in low contact resistance of the structure. Excessively high contact resistance causes two problems:
a) the contrast between the high resistance of an antifuse which is not short-circuited and the low resistance of a short-circuited antifuse is too small, which may lead to a read-out error when analyzing the state of the antifuse; and
b) the time constant when reading out the antifuse is too great, which lengthens access time to the part of the circuit selected by the antifuse.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for fabricating an integrated circuit and a corresponding integrated circuit in which the contact resistance is reduced. According to the invention, this object is achieved by a fabrication method comprising the steps of preparing a circuit substrate, providing a first metallization region comprising a first metal in the circuit in the substrate, depositing a first insulation layer over the entire surface of the substrate, providing a silicon layer on the first insulation layer, jointly patterning the silicon layer and the first insulation layer to form a stack comprising a first insulation region and the silicon region above the first metallization region, depositing a second metallization layer over the patterned first insulation region and silicon region, conditioning the stack to create a metal silicide out of the silicon region and the second metallization layer over the silicon region to form a conductive region, then etching the second metallization layer to remove that layer that remains laterally next to the conductive region of the metal silicide, providing a second insulating region above the first insulation region and the conductive region, forming a contact in the second insulation region in order to make contact with the conductive region and providing an interconnect for connection to the contact.
Thus, the method produces an integrated circuit having a circuit substrate with a first metallization region comprising a first metal in the circuit substrate, a first insulation region above the first metallization region, a conductive region comprising a metal silicide above the first insulation region, a second insulation region above the first insulation region and conductive region, a contact in the second insulation region and an interconnect for the cont
Infineon - Technologies AG
Rocchegiani Renzo
Schiff & Hardin LLP
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