Integrated circuit having amorphous silicide layer in contacts a

Details Integrated circuit having amorphous silicide layer in contacts a Integrated circuit having amorphous silicide layer in contacts a

1998-05-06

2000-02-22

Tran, Minh Loan

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257751, 257754, 257763, H01L 2348, H01L 2352, H01L 2940

Patent

active

060283599

ABSTRACT:
An integrated circuit, a contact and a method of manufacture therefor. The integrated circuit has a silicon substrate with a recess formed therein that provides an environment within which the contact is formed. The contact includes: (1) an adhesion layer deposited on an inner surface of the recess, (2) an amorphous layer, deposited over the adhesion layer within the recess and (3) a central plug, composed of a conductive material, deposited at least partially within the recess, the silicide layer being amorphous to prevent the conductive material from passing through the amorphous silicide layer to contact the adhesion layer thereby to prevent junction leakage.

REFERENCES:
patent: 4800176 (1989-01-01), Kakumu et al.
patent: 4960732 (1990-10-01), Dixit et al.
patent: 4962414 (1990-10-01), Liou et al.
patent: 4975753 (1990-12-01), Ema
patent: 4976839 (1990-12-01), Inoue
patent: 5106781 (1992-04-01), Penning De Vries
patent: 5322812 (1994-06-01), Dixit et al.
patent: 5332691 (1994-07-01), Kinoshita et al.
patent: 5355020 (1994-10-01), Lee et al.
patent: 5371041 (1994-12-01), Liou et al.
patent: 5380678 (1995-01-01), Yu et al.
patent: 5397742 (1995-03-01), Kim
patent: 5420074 (1995-05-01), Ohshima
patent: 5451551 (1995-09-01), Krishman et al.
patent: 5504038 (1996-04-01), Chien et al.
patent: 5514908 (1996-05-01), Liao et al.
patent: 5529955 (1996-06-01), Hibino et al.
patent: 5585308 (1996-12-01), Sardella
patent: 5591671 (1997-01-01), Kim et al.
patent: 5641985 (1997-06-01), Tamura
patent: 5851581 (1998-12-01), Zenke
Stanley Wolf Ph.D. & Richard N. Tauber, Ph.D., "Silicon Processing for the VLSI Era"; 1986 Lattice Press; pp. 331-335 and pp. 384-392.
Hyeongtag Jeon, Gangjoong Yoon, & R.J. Nemanich; Dependence of the C49-C54 TiSi.sub.2 phase transition temperature on film thickness and Si substrate orientation; 1997 Elsevier Science S.A.-Thin Solid Films 299; pp. 178-182.
J. Perez-Rigueiro, P. Herrero, C. Jimenez, R. Perez-Casero and J. M. Martinez-Duart; Characterization of the Interfaces Formed During the Silicidation Process of Ti Films on Si at Low and High Temperatures; Surface and Interface Analysis vol. 25-1997; pp. 896-903.

Affiliated with

Also associated with

Rating

Integrated circuit having amorphous silicide layer in contacts a does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated circuit having amorphous silicide layer in contacts a, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit having amorphous silicide layer in contacts a will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-522740