Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2003-03-28
2004-09-28
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S203000, C257S208000, C257S210000, C257S211000
Reexamination Certificate
active
06798069
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
This invention relates to integrated circuits, and more particularly to integrated circuit layout using multi-layer trace conductors extending from probe pads of the integrated circuit to accommodate dissimilar-sized core and input/output regions.
2. Description of Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
Integrated circuits have evolved over the years. In part, the enhancement in semiconductor components (e.g., smaller and faster transistors) has contributed to the increased functionality and speed of integrated circuits (ICs). Modem ICs have become denser in overall circuit components and employ smaller critical dimensions. Manufacturing of these modern ICs has also advanced in order to maintain pace with the growing number of components involved for each IC. As the IC becomes smaller in critical dimension and denser in circuitry, the number of bonding pads per IC has also increased.
Typically, the bonding pads of an IC are arranged on the periphery of that circuit. An IC can encompass a single die within a plurality of dice which form a wafer. Generally, the bonding pads are arranged near the outer edge of the die. The bonding pads extend along a single line, or axis, adjacent to each of the four edges of the die. In addition, the bonding pads can form a multitude of single lines parallel to a first single line that can encompass the circuit. Each of the bonding pads is exclusively reserved for a signal. Some bonding pads of the IC may be coupled to terminals of the device package configured to supply power and ground signals to the core of the IC, while other bonding pads are reserved for signals coming to or from the core. The core contains a plurality of circuitry adapted for a specific process. For example, an Application Specific Integrated Circuits (“ASIC”) chip has a plurality of circuits adapted to perform a specific function. The complexity of a core, therefore, is dependent on specific needs of an application.
The IC also includes an I/O ring which encompasses the perimeter of the core and typically lies in the outer periphery of the die. Within the I/O ring can be dedicated regions or slots. Each slot can contain an I/O circuit corresponding to a one bonding pad. The circuitry can be used to protect the integrity of the signal being received or sent from the core. For example, the circuitry can provide electrostatic discharge (ESD) protection or can be receivers, drivers, or buffers coupled to boost or isolate the path of a signal. In order to connect the bonding pads to the I/O ring or core, the IC includes a plurality of trace conductors. The trace conductors are metal wires printed onto the substrate and adapted to route a signal from a bonding pad to the core or I/O slot. However, as the die size of ICs decreases and the density of the core increasing, the routing of trace conductors has become more difficult. Constraints on the routing path due to the increase in I/O components (i.e., bonding pads, I/O circuitry, etc) needed to accommodate the increasing circuitry of the core have limited the use of multiple rows of bonding pads.
It would be desirable to provide a mechanism for routing the bonding pad rows to the I/O ring and core while maintaining signal integrity. It would further be desirable to effectively provide multiple rows of bonding pads to accommodate the high number of I/O circuitry while maintaining or decreasing the size of the die area. The desired improvements would, therefore, achieve an adequate means to increase manufacturing yield of a wafer.
SUMMARY OF THE INVENTION
The problems outlined above may be in large part addressed by an integrated circuit that includes multiple pad rows used to accommodate the evolving integrated circuits with small critical dimensions and dense circuitry. A plurality of trace conductors is used to interface a core or an Input/Output (I/O) ring to external peripheries of the integrated chips and are configured in multiple metal layers and possibly using different trace conductor widths.
In one embodiment, a first and second row of bonding pads are connected to a core and/or an I/O ring using a plurality of trace conductors. The core contains circuitry designed for specific application (i.e. an ASIC design). The I/O ring comprises a plurality of I/O circuits arranged along an axis parallel to the first and second row of bonding pads. Each I/O circuit is configured to couple with a corresponding bonding pad of either the first or second row and reserved for receiving a signal placed onto that bonding pad.
The first and second rows of bonding pads can be configured on separate metal layers, e.g., a first metal layer and a second metal layer, respectively. The first row of bonding pads encompasses all perimeters of a core and is situated closer to the interior of the IC. The second row of bonding pads is placed along an axis parallel to and dielectrically spaced from the first row and also is further from the interior of the IC. A first trace conductor can be arranged on the second metal layer extending from a first bonding pad within the second row. A second trace conductor configured on the second metal layer is extended from a second bonding pad within the second row. The first trace conductor can be routed between a first neighboring pair of the first row of bonding pads and connects the bonding pad to the I/O ring and/or core. In addition, the first trace conductor can be routed underneath the first row of bonding pads. Similarly, the second trace conductor, of differing width than the first trace conductor, is routed between a second neighboring pair of the first row of bonding pads towards the I/O ring or core and can be routed underneath the first row. The different widths of the trace conductors provide resistance compensation for signals that require differing input/output resistance. For instance, a power bonding pad and/or a ground bonding pad have constrained resistance requirements but may be located within the second row of the bonding pads. Extending the routing path of the power bonding pad and ground bonding pad increases the resistance, contrary to the lower resistance needed for such paths. By utilizing a wider metal layer, the resistance may be lowered, even for paths that extend to the more distal outer rows of bonding pads.
A third row of bonding pads can also be provided. The third row is situated along an axis parallel to the first and second rows and includes a plurality of trace conductors coupled to interface external peripheries to the core and/or I/O ring. The third row of bonding pads can be configured in a third metal layer, and has a third trace conductor extending from a bonding pad of the third row. The third trace conductor can contact to either the core or I/O ring using a via. The third trace conductor can be routed between a neighboring pair of bonding pads of the second row and a neighboring pair of bonding pads of the first row. For example, a trace conductor, dedicated to receiving a power supply can be within the third row to provide a power signal to the power supply conductor of an I/O ring. The via is extended between the third trace conductor and the power supply conductor, providing contact between different metal layers. In addition, the third trace conductor may further extend into a core through a via to deliver the power signal to the core.
In an alternative embodiment, the first, second, and third bonding rows are configured on the same metal layer, e.g., a first metal layer. The first, second, and third trace conductors are used to route between the bonding pads and the I/O ring and/or core in a second metal layer dielectrically spaced beneath the first metal layer. A via is used in order for a contact to be made between the bonding rows and the trace conductors. For example, to contact a trace conductor from the second metal layer to a bonding pad in the second row configured in the first metal layer, a via is extended
Ali Anwar
Doddapaneni Kalyan
Lau Tauman T.
Conley & Rose, P.C.
Flynn Nathan J.
Greene Pershelle
LSI Logic Corporation
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