Integrated circuit having a sublayer electrical contact and fabr

Details Integrated circuit having a sublayer electrical contact and fabr Integrated circuit having a sublayer electrical contact and fabr

1981-06-30

1984-05-01

James, Andrew J.

357 68, 357 49, 357 71, 357 48, H01L 2348, H01L 2946, H01L 2962, H01L 2712

Patent

active

044464762

ABSTRACT:
An integrated circuit containing a refractory metallic silicide beneath a field isolation region and in electrical contact with electrical conductive regions of active impurity dopants in a semiconductive substrate; and process for the fabrication thereof.

REFERENCES:
patent: 3381182 (1968-04-01), Thornton
patent: 3653120 (1972-04-01), Sirrine et al.
patent: 3659162 (1972-04-01), Toshio et al.
patent: 3908187 (1975-09-01), Sheldon et al.
patent: 4081823 (1978-03-01), Cook, Jr.
patent: 4128670 (1978-12-01), Gaensslen
patent: 4157269 (1979-06-01), Ning et al.
patent: 4234362 (1980-11-01), Riseman
patent: 4385433 (1983-05-01), Ozawa
1980 International Electron Devices Meeting (IEDM) Technical Digest, "Self-Aligned NPN Bipolar Transistors", pp. 823-824, Ning et al.
Appl. Phys. Lett. 37(3), Aug. 1, 1980, "Refractory Metal Silicide Formation Induced by AS+ Implantation", pp. 295-298, Tsai et al.
J. Appl. Phys. 50(10), Oct. 1979, "Silicide Formation by High-Dose Si+-ion Implantation of Pd", pp. 6321-6327, Chapman et al.

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