Integrated circuit having a parasitic resonance filter

Details Integrated circuit having a parasitic resonance filter Integrated circuit having a parasitic resonance filter

1997-02-18

1999-06-29

Brown, Peter Toby

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

257724, 257728, 257665, H01L 23495

Patent

active

059172339

ABSTRACT:
A packaged integrated circuit configured for interconnection to an external component comprises a die (1) having a high frequency contact (8), the die (1) being disposed on a lead frame (3). The lead frame (3) comprises a plurality of leads (9). At least two of the leads are first and second RF port leads (9a, 9b) which are electrically connected to the RF port. When mounted to a printed circuit board substrate, there is a capacitor (12) connected between the first and second high frequency contact (8) leads (9a, 9b) to achieve frequency specific signal attenuation at an unwanted frequency with minimal contribution of insertion loss at a desired frequency.

REFERENCES:
patent: 5220298 (1993-06-01), Nagase
patent: 5495125 (1996-02-01), Uemura
patent: 5635751 (1997-06-01), Ikeda et al.
Patent Abstracts of Japan, Application Date Aug. 26, 1991, Application Number 03213409.
PCT Search Report, dated Jul. 15, 1998, PCT/US 98/03290.
Publication Title: Wireless Systems Design; Authors: Theodore J. Kalinka and Thomas W. Baker; Article Title: Minimizing GSM Mobile-Terminal Design Risk Allows Easier Upgrades; Date of Article: May, 1996; Pertinent pp.: 54 And 55;.

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