Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2007-09-18
2007-09-18
Phung, Anh (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185250, C365S185330
Reexamination Certificate
active
11120270
ABSTRACT:
An integrated circuit includes a memory (10). The memory (10) includes an array (12) of non-volatile memory cells. Each memory cell (14) of the array (12) includes a plurality of terminals comprising: a control gate, a charge storage region, a source, a drain, a well terminal, and a deep well terminal. Following an erase operation of the array (12), the erase voltages are discharged from each of the memory cells. A discharge rate control circuit (11) controls the discharging of terminals of the memory cell. The discharge rate control circuit (11) includes, for example, a plurality of parallel-connected transistors (112) coupled between the array (12) of non-volatile memory cells and a power supply terminal.
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Hill Daniel D.
Luu Pho M.
Phung Anh
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