Static information storage and retrieval – Powering
Reexamination Certificate
2007-11-06
2007-11-06
Tran, Michael T (Department: 2827)
Static information storage and retrieval
Powering
C365S203000
Reexamination Certificate
active
11427610
ABSTRACT:
An integrated circuit with a low voltage read/write operation is provided. The integrated circuit may include a processor and a plurality of memory cells organized in rows and columns and coupled to the processor, wherein a row of memory cells comprises a word line and all of the memory cells coupled to the word line, and wherein a column of memory cells comprises a bit line and all of the memory cells coupled to the bit line. The integrated circuit may further include a first power supply voltage terminal for receiving a first power supply voltage, wherein the first power supply voltage is provided to power the processor, and wherein the first power supply voltage is provided to power the plurality of memory cells during a first access operation of the plurality of memory cells. The integrated circuit may further include a second power supply voltage terminal for receiving a second power supply voltage higher than the first power supply voltage, wherein the second power supply voltage is provided to power the plurality of memory cells during a second access operation of the plurality of memory cells.
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Kevin Zhang, Uddalak Bhattacharya, Zhanping Chen, Faith Hamzaoglu, Daniel Murray, Narendra Vallepalli, Yih Wang, Bo Zheng, and Mark Bohr, “A 3-GHz 70-Mb SRAM in 65-nm CMOS Technology With Integrated Column-Based Dynamic Power Supply,” IEEE Journal of Solid-State Circuits, vol. 41, No. 1, Jan. 2006, pp. 146-151.
Bearden David R.
Burnett James D.
Cooper Troy L.
Kenkare Prashant U.
Russell Andrew C.
Freescale Semiconductor Inc.
Hill Daniel
Singh Ranjeev
Tran Michael T
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