Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2000-02-22
2001-01-23
Quach, T. N. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S775000, C438S381000, C438S671000, C438S673000
Reexamination Certificate
active
06177715
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to an integrated circuit comprising at least one level of metallization, the level of metallization being provided with tracks and comprising metal portions of at least two different thicknesses.
A level of metallization usually comprises metal tracks of small thickness, for example 1 micron, and small width, for example
1
micron. These metal tracks are used to transfer logic data. To manufacture inductors with an inductance of several nanohenrys, a separate level of metallization may be provided which is employed only for this purpose. In order to reduce the resistance of these inductors, particularly the direct-current resistance, use is made of inductors having a large width of, for example, 20 &mgr;m, and a large thickness of, for example, 2.5 &mgr;m.
However, it is rather unsatisfactory to use a level of metallization only for inductors as a large area of this level of metallization remains unused. For this reason it would be desirable to take measures enabling said level of metallization to also comprise tracks for the transfer of logic data, said tracks having a small width. However, it is very difficult to manufacture tracks which are narrow and thick.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an integrated circuit having a level of metallization comprising both an inductor and a track for, for example, transfer of logic data.
To achieve this, the integrated circuit in accordance with the invention is characterized in that the level of metallization comprises at the same time at least one inductor and at least one track, the track being formed on a portion of small thickness, and the inductor being formed on a portion of large thickness.
The coupling between the turns of wire of the inductor is only slightly affected by the profiles of the portions having a large thickness, which include a first part at the bottom of the step having a straight edge and a second concave part.
In an embodiment of the invention, the level of metallization comprises a first metal layer and a second metal layer, which are separated by a stop layer. The second metal layer may have a larger thickness than the first metal layer.
A further object of the invention is to provide a method of manufacturing a level of metallization of an integrated circuit, the level of metallization being provided with tracks. A first metal layer is provided, whereafter a stop layer and a second metal layer are applied. A first mask of a resin is provided on the circuit. The second metal layer is subjected to photoetching down to the stop layer. A second resin mask is deposited on the circuit. The stop layer and the first metal layer are etched, in such a manner that portions comprising the first metal layer and the second metal layer and portions comprising only the first metal layer remain intact.
After photoetching the second metal layer, the first mask may be removed or preserved.
In this manner, an integrated circuit is obtained wherein the use of a level of metallization is optimized, which enables the number of levels of metallization to be reduced, resulting in a smaller thickness of the integrated circuit and in a saving in costs owing to the smaller number of process steps, or, the performance of the integrated circuit to be increased if the number of levels of metallization remains unchanged.
These and other aspects of the invention will be apparent from and elucidated, by way of non-limitative example, with reference to the embodiment(s) described hereinafter.
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patent: 4914056 (1990-04-01), Okumura
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patent: 5370766 (1994-12-01), Desaigoudar et al.
patent: 5384274 (1995-01-01), Kanechachi
patent: 5652157 (1997-07-01), Hirano et al.
patent: 5930637 (1999-07-01), Chuang et al.
patent: 5936299 (1999-08-01), Burghartz et al.
patent: 0471376 A2 (1992-02-01), None
patent: 0706211 A2 (1996-04-01), None
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International Search Report PCT/IB 99/01129.
Louwers Stephan
Marty Michel
Biren Steven R.
Quach T. N.
U.S. Philips Corporation
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