Integrated circuit having a dummy structure and method of making

Details Integrated circuit having a dummy structure and method of making Integrated circuit having a dummy structure and method of making

1996-08-21

1999-03-23

Fourson, George

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

With electrical circuit layout

438424, 438692, 364491, H01L 2176, H01L 2170

Patent

active

058858563

ABSTRACT:
A pattern of dummy structures (20) is added to the layout pattern of an integrated circuit (10) to equilibrate the polishing rate across the surface of a semiconductor substrate (11). The location of each dummy structure (20) is predetermined so that it does not intersect a well boundary (17) or an active region (21,27), and does not fall under a conductive material such as a layer of polysilicon (22,28) or an interconnect structure (23,29).

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patent: 5498565 (1996-03-01), Gocho et al.
Wolf, S. "Silicon Processing for the VLSI Era:vol. 2, Process Integration", Lattice Press, 1990, p. 54.

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