Integrated circuit having a cascode current mirror

Details Integrated circuit having a cascode current mirror Integrated circuit having a cascode current mirror

1994-02-14

1994-12-13

Stephan, Steven L.

Electricity: power supply or regulation systems

Self-regulating

Using a three or more terminal semiconductive device as the...

323316, 330288, G05F 316, H03F 304

Patent

active

053732286

ABSTRACT:
An integrated circuit comprising a cascode current mirror and a bias stage for biassing the cascode current mirror, the cascode current mirror comprising, between an input terminal (11) and a supply voltage terminal (14), a first cascoded MOS transistor (21) and a first cascode MOS transistor (22) and, between an output terminal (12) and the supply voltage terminal (14), a second cascoded MOS transistor (23) and a second cascode MOS transistor (24). In order to obtain a minimal voltage between the output terminal (12) and the supply voltage terminal (14) the bias stage comprises a first bias current source (31) for generating a first bias current, a second bias current source (32) for generating a second bias current, a first bias MOS transistor (41) having a gate coupled to the gates of the two cascoded MOS transistors (21, 23), a source, and a drain coupled to the first supply voltage terminal (13) via the first bias current source (31), a second bias MOS transistor (42) having a gate coupled to the gates of the two cascode MOS transistors (22, 24), a source coupled to the source of the first bias MOS transistor (41), and a drain coupled to the first supply voltage terminal (13) via the second bias current source (32), and a third bias MOS transistor (43) coupled between the sources of the two bias MOS transistors (41, 42) and the second supply voltage terminal (14).

REFERENCES:
patent: 4477782 (1984-10-01), Swanson
patent: 4550284 (1985-10-01), Sooch
patent: 4618815 (1986-10-01), Swanson
patent: 4866368 (1989-09-01), Bird
patent: 4983929 (1991-01-01), Real et al.
patent: 5311115 (1994-05-01), Archer

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