Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
1999-05-12
2001-08-07
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C438S132000, C438S467000
Reexamination Certificate
active
06271574
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of integrated circuits, and, more particularly, to an integrated circuit fuse.
BACKGROUND OF THE INVENTION
Providing fuses in integrated circuits is a practice well-known to those skilled in the art, especially in the manufacture of MOS circuits. For example, it is standard practice to provide fuses to protect MOS transistor gates against the accumulation of electrostatic charges which appear during the manufacture of integrated circuits. These fuses are then disrupted or fused to release the gates of the transistors. As another example, providing redundant word lines or bit lines in large capacity memories also relies on the use of fuses. The defective or unnecessarily redundant lines are then isolated from the rest of the memory by fusing or disrupting the fuses. In general, integrated circuit fuses are designed to be disrupted by the application of a fusing voltage or current to enable the modification of the configuration of a circuit at a final stage of manufacture.
A prior art fuse made by etching is of the type shown in
FIG. 1. A
fuse
1
of this kind, with a very simple structure and a small space requirement, includes a small bar-shaped central region
2
that widens out at its ends to form two zones
3
,
4
receiving a plurality of electrical contacts
5
,
6
. In general, as can be seen in
FIG. 2
in a sectional view, the fuse
1
is buried in an integrated circuit
10
where it is sandwiched between a lower layer
11
and an upper layer
12
of oxide deposited on a silicon substrate
13
. The contacts
5
,
6
take the form of metallized holes going through the oxide layer
12
to connect the zones
3
,
4
to conductors
14
,
15
. Conventionally, the whole unit is made by the successive deposition of various layers of oxide, metal and/or polysilicon and by the etching of the layers by photolithography.
In order that the current density in the fuse
1
and the efficiency of the fusing may be a maximum for a given fusing current, the width W of the central region
2
of the fuse is usually chosen to be equal to the technological minimum width W
min
permitted by the manufacturing technology of the integrated circuit
10
. For example, at present, the technological minimum width W
min
of the MOS type integrated circuits is commonly about 0.25 micrometers with respect to the minimum width of a conductor, i.e., the minimum length of the gates of the MOS transistors.
However, this precaution provides only a relative advantage, given that the technological minimum also determines the size of the other components present in the integrated circuit
10
. This is particularly true with transistors, and their capacity to withstand high voltages or currents. Thus, in recent years, the reduction of the technological minimum width through the improvement of technologies has gone hand in hand with a reduction of the permissible fusing voltages and currents. For example, the maximum fusing voltages permitted in medium-scale integrated MOS circuits according to older technology were in the range of 5.5 to 6 volts. For large-scale integrated circuits formed using current technology, the maximum fusing voltages are no more than 1.8 to 2 volts.
Despite providing for a minimum width, a standard fuse does not, in statistical terms, provide a fusing efficiency equal to 100% under standard fusing conditions. In other words, when it is sought to simultaneously fuse or disrupt a set of fuses present in an integrated circuit by applying one or more fusing pulses of current or voltage, it frequently happens that non-disrupted fuses remain. These fuses have an electrical resistance which, although it is higher than their initial electrical resistance, cannot be compared to that of an open circuit. This drawback is reflected in the efficiency of manufacture of the integrated circuits, and becomes more of problem when several tens or even several hundreds of fuses are to be made in the same integrated circuit.
The technological minimum width W
min
therefore, represents an obstacle in the search for a fuse having high fusing efficiency. It is well known in the field of photolithography that the technological minimum width W
min
is determined by various technological constraints. In particular, obtaining satisfactory reliability of the gates of the MOS transistors is determined by the technological minimum width W
min
. Furthermore, a phenomenon of diffraction and reflection of light during the isolation of the organic resin etching masks exists, and is known to those skilled in the art as the “proximity optical effect”.
Finally, another drawback of standard integrated circuit fuses is that they are not entirely reliable. A certain percentage of disrupted fuses have a tendency to regenerate for reasons as yet poorly explained. The regeneration of a fuse is expressed by the fact that its electrical insulation properties deteriorate, whereas they were initially satisfactory.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an integrated circuit fuse capable of being more easily fused than a standard fuse when conducting an identical current.
Another object of the present invention is to provide a fuse having a fusing efficiency greater than that of standard fuses along with improved reliability.
Yet another object of the present invention is to provide an integrated circuit fuse having a width smaller than a technological minimum width, and a method for manufacturing such a fuse.
These objects are achieved by providing an integrated circuit fuse including a substantially bar-shaped central region and zones including electrical contacts in which the central region has a thinned zone. A smaller width forms a weak point facilitating fusing of the fuse through an increase in the local current density in standard fusing conditions.
The fuse is obtained by photolithography and includes at least one dummy element in the vicinity of the thinned zone. The thinning of the central region is obtained by optical proximity effect between at least one edge of the central region and one edge of the dummy element. Advantageously, the width of the thinned zone is smaller than a technological minimum width used for manufacturing the integrated circuit. The width of the central region outside the thinned zone is substantially equal to the technological minimum width.
According to one embodiment, the thinned zone is substantially symmetrical with respect to the longitudinal axis of the central region, and is formed by two notches made in the edges of the central region.
According to another embodiment, the fuse includes two dummy elements on each side of the thinned zone.
According to yet another embodiment, the fuse is made out of polysilicon.
According to another embodiment, the fuse includes oxide spacers that do not entirely overlap the edges of the thinned zone.
According to another embodiment, the contacts are metallized holes going through an oxide layer covering the fuse to connect the zones of the fuse with the conductive elements.
According to still yet another embodiment, the increase in the electrical resistance of the central region due to the thinned zone is negligible as compared with the total resistance of the fuse. The total resistance includes the resistance of access to the fuse. The access resistance includes the electrical resistance of conductive elements and the electrical resistance of the contacts.
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patent: 5208124 (1993-05-01), Sporon-Fiedler et al.
patent: 5589706 (1996-12-01), Mitwalsky et al.
patent: 5608257 (1997-03-01), Lee et al.
patent: 5708291 (1998-01-01), Bohr et al.
patent: 5970346 (1999-10-01), Liaw
patent: 6008716 (1999-12-01), Kokubun
patent: 0 313 815 A2 (1988-09-01), None
patent: 2 758 007 (1997-12-01), None
patent: 1-169942 (1989-07-01), None
Mohsen Alavi et al., “A PROM Element Based on Salicide Agglomeration of Poly Fuses in a CMOS Logic Process” IE DM97 (Dec. 1997) pp. 855-858.
Delpech Philippe
Revil Nathalie
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Crane Sara
Galanthay Theodore E.
STMicroelectronics S.A.
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