Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
1999-05-04
2002-10-22
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C438S132000, C438S215000, C438S281000, C438S333000, C438S467000, C438S601000
Reexamination Certificate
active
06469363
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of integrated circuits and, more particularly, to an integrated circuit fuse.
BACKGROUND OF THE INVENTION
Forming fuses in integrated circuits is a practice well-known to those skilled in the art, especially in the manufacture of metal oxide semiconductor (MOS) circuits. For example, it is standard practice to form fuses to protect MOS transistor gates against the accumulation of electrostatic charges that appear during the manufacture of integrated circuits. These fuses are then disrupted or fused to release the gates of the transistors. Providing redundant word lines or bit lines in large capacity memories also rely on the use of fuses. The defective or unnecessary and redundant lines are then cut off from the rest of the memory by the fusing or disrupting of fuses.
Thus, in general, the fuses present in integrated circuits are designed to be fused by the application of a fusing voltage or current which enables modification of the configuration of a circuit at a final stage of manufacture.
A prior art fuse
1
of the type shown in
FIG. 1
includes a central region
2
in the shape of a small bar that widens out at its ends to form two zones
3
,
4
receiving a plurality of electrical contacts
5
,
6
. In general, as can be seen in
FIG. 2
in a sectional view, the fuse
1
is buried in an integrated circuit
10
where it is sandwiched between a lower oxide layer
11
and an upper oxide layer
12
that are deposited on a silicon substrate
13
. The contacts
5
,
6
take the form of metallized holes going through the oxide layer
12
to connect the zones
3
,
4
to respective conductors
14
,
15
. The whole unit is made in a standard way by the successive deposition of various layers of oxide, metal and/or polysilicon, and by the etching of the layers by photolithography.
In order that the current density in the fuse
1
and the efficiency of the fusing may be a maximum for a given fusing current, the width W of the central region
2
of the fuse is usually chosen to be equal to the minimum width W
min
permitted by the manufacturing technology of the integrated circuit
10
. For example, at present, a minimum width W
min
of a conductor for MOS type integrated circuits is commonly about 0.25 micrometers.
However, this precaution provides only a relative advantage, given that the minimum width determines the size of the other components present in the integrated circuit
10
. This is particularly so for transistors, and their capacity to withstand high voltages or currents. Thus, in recent years, the reduction of the minimum width of a conductor as a result of advancements in manufacturing technology has gone hand in hand with a reduction in the permissible fusing voltages and currents. For example, the maximum fusing voltages permitted in medium-scale integrated MOS circuits according of the prior art technology were in the range of 5.5 to 6 volts. Today, large-scale integrated circuits using the most current technology have maximum fusing voltages of no more than 1.8 to 2 volts.
Thus, despite providing for a minimum width, a standard fuse does not, in statistical terms, provide a fusing efficiency equal to 100% under standard fusing conditions. In other words, to simultaneously fuse or disrupt a set of fuses present in an integrated circuit by applying one or more fusing pulses of current or voltage, it frequently happens that non-disrupted fuses remain. These fuses have an electrical resistance which, although it is higher than their initial electrical resistance, cannot be equal to that of an open circuit.
This drawback effects the efficiency in the manufacture of the integrated circuits, and becomes a significant problem when several tens, or even several hundreds of fuses are formed in the same integrated circuit. Another drawback of standard fuses is that they are not entirely reliable. A certain percentage of disrupted fuses have a tendency to regenerate, for reasons as yet poorly explained. In practice, the regeneration of a fuse is expressed by the fact that its electrical insulation properties deteriorate, whereas they were initially satisfactory.
Finally, the fusing current that can be applied to a fuse without going beyond a given fusing voltage is limited by the presence of parasitic resistors forming an access resistance to the fuse. It is known that the access resistance of a fuse includes the resistance of the electrical contacts
5
,
6
, which is generally in the range of 5&OHgr; per contact, and the resistance of the zones
3
,
4
between the contacts and the central region. The increase in the number of contacts makes it possible to reduce the access resistance. However, the number of contacts that can be planned remains limited by the small width of the central region
2
and the distribution of the current in the zones
3
,
4
. In other words, the widening of the zones
3
,
4
to add yet additional contacts would not modify the access resistance.
SUMMARY OF THE INVENTION
An objective of the present invention is to provide an integrated circuit fuse that is fused more easily than a standard prior art fuse. An integrated circuit fuse according to the present invention reduces the fusing voltage applied to the terminals of the fuse, which correlates with the trend towards reducing supply voltages of integrated circuits.
Another object of the present invention is to provide an integrated circuit fuse that has increased fusing efficiency and reliability as compared to standard fuses.
Yet another object of the present invention is to provide an integrated circuit fuse with low access resistance.
These objects are achieved by providing an integrated circuit fuse formed on a substrate by etching a layer of polysilicon, metal or alloy to include a central region, at the end of which are zones with electrical contacts. The central region has at least two first electrically parallel arms. A zone of intersection of the first two arms forms a point for focusing a fusing current which facilitates the fusing of the fuse by increasing the local current density.
According to one embodiment, the central region includes, beyond the intersection zone, two second arms positioned as a prolongation of the first two arms. Depending on the chosen embodiment, the arms may be arranged at right angles, and/or have the same length, and/or have the same width. Preferably, the arms have a width equal to a minimum width according to current manufacturing standards available for manufacturing integrated circuit fuses.
REFERENCES:
patent: 5444287 (1995-08-01), Bezama et al.
patent: 5572050 (1996-11-01), Cohen
patent: 5659182 (1997-08-01), Cohen
patent: 5708291 (1998-01-01), Bohr et al.
patent: 5798534 (1998-08-01), Young
patent: 2-186660 (1990-07-01), None
Delpech Philippe
Revil Nathalie
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Chaudhuri Olik
Jorgenson Lisa K.
Louie Wai-Sing
STMicroelectronics S.A.
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