Integrated circuit formed with shallow isolation structures havi

Details Integrated circuit formed with shallow isolation structures havi Integrated circuit formed with shallow isolation structures havi

1997-02-11

1999-07-13

Bowers, Charles

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

438221, 438218, H01L 4900, H01L 2702, H01L 2978

Patent

active

059239921

ABSTRACT:
A method for protecting the trench dielectric fill for a shallow trench isolation structure by forming a protective layer upon the upper surface of the trench dielectric is presented. In a preferred embodiment, the protective layer comprises a layer of nitride formed upon a layer of oxide. Various etch and cleaning processes during the semiconductor device formation may cause damage to the trench dielectric. A shallow trench is typically formed early in the process sequence. A trench dielectric is deposited into the shallow trench and then planarized so that the upper surface of the trench dielectric is at the same level as the upper surface of the trench dielectric. Damage to the upper surface of the trench dielectric may be caused during several of the subsequent processing steps, including: the etch process used to form the polysilicon gate; the etch process used to form oxide spacers upon the sidewall surfaces of the conductive structures; the etch process used to form contact holes through interlevel dielectrics; and the metal deposition into the contact holes used to establish an electrical contact with the conductive structures. By forming a protective nitride layer upon the upper surface of the trench dielectric, the trench dielectric is better protected against damage.

REFERENCES:
patent: 4729006 (1988-03-01), Dally et al.
patent: 5433794 (1995-07-01), Fazan et al.
patent: 5733383 (1998-03-01), Fazan et al.

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