Integrated circuit formed on a semiconductor substrate with a va

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307246, 307451, 307469, 307585, 307268, 307591, H03K 494, H03K 501

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active

044993870

ABSTRACT:
A MOS type semiconductor integrated circuit comprising a C-MOS inverter including P- and N-channel MOS transistors connected in series between V.sub.DD and V.sub.SS power supply terminals, the gates of the MOS transistors being supplied with an input signal; a variable capacitor connected between a node at which the transistors are interconnected and a reference voltage; and a voltage generator for producing an output voltage to the variable capacitor, the voltage generator being capable of irreversibly changing the level of the output voltage, thereby changing a capacitance of the variable capacitor.

REFERENCES:
patent: 3852619 (1974-12-01), Carbrey
patent: 3872321 (1975-03-01), Matsue
patent: 3944848 (1976-03-01), Heeren
patent: 4130766 (1978-12-01), Patel et al.
patent: 4346310 (1982-08-01), Carter
patent: 4393318 (1983-07-01), Takahashi et al.
patent: 4424456 (1984-01-01), Shiraki et al.
patent: 4455495 (1984-06-01), Masuhara et al.
Kokkonen et al., "Redundancy Techniques for Fast Static RAMs"; ISSCC 81/Wednesday, Feb. 18, 1981, IEEE International Solid-State Conference, pp. 80-81.

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