Integrated circuit for transferring complementary charge packets

Details Integrated circuit for transferring complementary charge packets Integrated circuit for transferring complementary charge packets

1980-07-11

1982-09-14

Munson, Gene M.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

357 24, G11C 1928, H01L 2978

Patent

active

043497497

ABSTRACT:
An integrated circuit for transferring complementary charge packets between a first and second charge transfer device has a resettable gate common to both charge transfer devices which serves as a transfer electrode for the first charge transfer device and as an electrode in the input stage of the second charge transfer device. An electrode which is maintained at a constant voltage is disposed in the second charge transfer device between the common electrode and an oppositely doped semiconductor region which is connected to a normally constant voltage which periodically is substantially reduced, thereby flooding the region beneath the common electrode with charge carriers. When the voltage connected to the oppositely doped semiconductor region is returned to a high value, a potential well is created beneath the constant voltage electrode which becomes filled with a first charge packet. Upon the appearance of the charge packet in the first transfer device beneath the common electrode, a voltage drop occurs which results in a corresponding potential drop beneath the common gate in the second charge transfer device resulting in a flow of charge carriers in reverse to the previous flow leaving a charge packet beneath the common gate which is complementary to the charge packet introduced into the first charge transfer device.

REFERENCES:
patent: 3867645 (1975-02-01), Weimer
patent: 4040077 (1977-08-01), Tehon
patent: 4099197 (1978-07-01), Ibrahim et al.
patent: 4210825 (1980-07-01), Crochiere et al.
Sequin et al., Charge Transfer Devices, Academic Press, N.Y., 1975, pp. 52-59.
Sealer et al., "A Dual Differential Charge-Coupled Analog Delay Device", IEEE J. Solid-State Circuits, vol. 5C-11 (2/76), pp. 105-108.

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