Integrated circuit for the programming of a memory cell in a non

Details Integrated circuit for the programming of a memory cell in a non Integrated circuit for the programming of a memory cell in a non

1996-04-18

1997-07-01

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular connection

36518507, 365200, G11C 1140

Patent

active

056445296

ABSTRACT:
In an integrated circuit for programming a memory cell in a non-volatile memory register which is associated with a memory matrix wherein the non-volatile memory register is used to store a redundancy address, the memory cell has at least one programmable non-volatile memory element having a control electrode and a data electrode and is suitable to store one bit of information. A load circuit associated to the memory element reads the information stored therein. The integrated circuit has switching means connected in series between the data electrode and a respective address signal line of an address signal bus which also supplies a decoding circuitry of the memory matrix. The switching means are controlled by a signal which determines the switching means to electrically connect the data electrode of the memory element to the address signal line when the memory cell of the non-volatile memory register is to be programmed, and to electrically disconnect the data electrode of the memory element from the address signal line when the information stored in the memory element is to be read by the load circuit.

REFERENCES:
patent: 4347483 (1982-08-01), Torimatu
patent: 4546454 (1985-10-01), Gupta et al.
patent: 4580247 (1986-04-01), Adam
patent: 5251169 (1993-10-01), Josephson
Cioaca, Dumitru et al., "A Million-Cycle CMOS 256K EEPROM," IEEE Journal of Solid-State Circuits, SC-22(5):684-692, Oct. 1987.
Vancu, Radu et al., "THAM 10.5: A 30ns Fault Tolerant 16K CMOS EEPROM," IEEE International Solid State Circuits Conference, New York, Feb. 1988, vol. 31, pp. 128-129, and 328.
Umezawa, Akira et al., "A 5-V-Only Operation 0.6 .mu.m Flash EEPROM with Row Decoder Scheme in Triple-Well Structure," IEEE Journal of Solid-State Circuits 27(11):1540-1545, Nov. 1992.

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